Patents by Inventor Ryuji Shibata

Ryuji Shibata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8068639
    Abstract: An image pickup apparatus includes: a face detection section configured to detect a face area from an image obtained by the image pickup apparatus; and a control section configured to detect at least any one of the amount of change in size of the face area detected by the face detection section and a movement speed of the face area, determine whether there is a possibility of occurrence of subject shake blur, which is blur occurring in a captured image due to the movement of a subject, on the basis of information on the detected amount of change in size of the face area or the detected movement speed of the face area, and output a warning when it is determined that there is a possibility of occurrence of subject shake blur.
    Type: Grant
    Filed: July 3, 2007
    Date of Patent: November 29, 2011
    Assignee: Sony Corporation
    Inventors: Hisashi Ishiwata, Yoshito Terashima, Tetsuo Mise, Ryuji Shibata, Masakazu Koyanagi
  • Publication number: 20110175634
    Abstract: To permit electrical testing of a semiconductor integrated circuit device having test pads disposed at narrow pitches probes in a pyramid or trapezoidal pyramid form are formed from metal films formed by stacking a rhodium film and a nickel film successively. Via through-holes are formed in a polyimide film between interconnects and the metal films, and the interconnects are electrically connected to the metal films. A plane pattern of one of the metal films equipped with one probe and through-hole is obtained by turning a plane pattern of the other metal film equipped with the other probe and through-hole through a predetermined angle.
    Type: Application
    Filed: March 30, 2011
    Publication date: July 21, 2011
    Inventors: Masayoshi Okamoto, Yoshiaki Hasegawa, Yasuhiro Motoyama, Hideyuki Matsumoto, Shingo Yorisaki, Akio Hasebe, Ryuji Shibata, Yasunori Narizuka, Akira Yabushita, Toshiyuki Majima
  • Publication number: 20110136272
    Abstract: To permit electrical testing of a semiconductor integrated circuit device having test pads disposed at narrow pitches probes in a pyramid or trapezoidal pyramid form are formed from metal films formed by stacking a rhodium film and a nickel film successively. Via through-holes are formed in a polyimide film between interconnects and the metal films, and the interconnects are electrically connected to the metal films. A plane pattern of one of the metal films equipped with one probe and through-hole is obtained by turning a plane pattern of the other metal film equipped with the other probe and through-hole through a predetermined angle.
    Type: Application
    Filed: February 1, 2011
    Publication date: June 9, 2011
    Inventors: Masayoshi OKAMOTO, Yoshiaki HASEGAWA, Yasuhiro MOTOYAMA, Hideyuki MATSUMOTO, Shingo YORISAKI, Akio HASEBE, Ryuji SHIBATA, Yasunori NARIZUKA, Akira YABUSHITA, Toshiyuki MAJIMA
  • Patent number: 7901958
    Abstract: To permit electrical testing of a semiconductor integrated circuit device having test pads disposed at narrow pitches probes in a pyramid or trapezoidal pyramid form are formed from metal films formed by stacking a rhodium film and a nickel film successively. Via through-holes are formed in a polyimide film between interconnects and the metal films, and the interconnects are electrically connected to the metal films. A plane pattern of one of the metal films equipped with one probe and through-hole is obtained by turning a plane pattern of the other metal film equipped with the other probe and through-hole through a predetermined angle.
    Type: Grant
    Filed: August 10, 2010
    Date of Patent: March 8, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Masayoshi Okamoto, Yoshiaki Hasegawa, Yasuhiro Motoyama, Hideyuki Matsumoto, Shingo Yorisaki, Akio Hasebe, Ryuji Shibata, Yasunori Narizuka, Akira Yabushita, Toshiyuki Majima
  • Publication number: 20100304510
    Abstract: To permit electrical testing of a semiconductor integrated circuit device having test pads disposed at narrow pitches probes in a pyramid or trapezoidal pyramid form are formed from metal films formed by stacking a rhodium film and a nickel film successively. Via through-holes are formed in a polyimide film between interconnects and the metal films, and the interconnects are electrically connected to the metal films. A plane pattern of one of the metal films equipped with one probe and through-hole is obtained by turning a plane pattern of the other metal film equipped with the other probe and through-hole through a predetermined angle.
    Type: Application
    Filed: August 10, 2010
    Publication date: December 2, 2010
    Inventors: Masayoshi OKAMOTO, Yoshiaki Hasegawa, Yasuhiro Motoyama, Hideyuki Matsumoto, Shingo Yorisaki, Akio Hasebe, Ryuji Shibata, Yasunori Narizuka, Akira Yabushita, Toshiyuki Majima
  • Patent number: 7642601
    Abstract: In a semiconductor integrated circuit device and a method of designing the same, design information about circuit cells each having a desired function are described as objects according to selected purposes. The pieces of design information are registered in a cell library as cell information capable of forming any of substrate potential fixed cells and substrate potential variable cells. Further, a data sheet common to the substrate potential fixed cell and the substrate potential variable cell is offered to a user, so that the user is able to make a selection according to the user's purposes. The substrate potential fixed cells and the substrate potential variable cells are mixed together on a semiconductor chip so as to be properly used according to the functions or the like of circuit portions in which the cells are used.
    Type: Grant
    Filed: May 18, 2009
    Date of Patent: January 5, 2010
    Assignee: Renesas Technology Corp.
    Inventors: Ryuji Shibata, Shigeru Shimada
  • Publication number: 20090278976
    Abstract: A drive control unit of the present invention includes: a first external force detecting section for detecting that an external force is applied to a first moving object body movable back and forth in a single direction; and a second initialization processing section which when it is detected that the external force is applied to the first moving object body by the first external force detecting section, moves at least one of second moving object bodies movable back and forth in the single direction to a predetermined second initial position and when it is not detected that the external force is applied to the first moving object body, does not move the second moving object body.
    Type: Application
    Filed: April 22, 2009
    Publication date: November 12, 2009
    Applicant: Sony Corporation
    Inventor: Ryuji Shibata
  • Publication number: 20090218626
    Abstract: In a semiconductor integrated circuit device and a method of designing the same, design information about circuit cells each having a desired function are described as objects according to selected purposes. The pieces of design information are registered in a cell library as cell information capable of forming any of substrate potential fixed cells and substrate potential variable cells. Further, a data sheet common to the substrate potential fixed cell and the substrate potential variable cell is offered to a user, so that the user is able to make a selection according to the user's purposes. The substrate potential fixed cells and the substrate potential variable cells are mixed together on a semiconductor chip so as to be properly used according to the functions or the like of circuit portions in which the cells are used.
    Type: Application
    Filed: May 18, 2009
    Publication date: September 3, 2009
    Inventors: Ryuji SHIBATA, Shigeru Shimada
  • Patent number: 7541647
    Abstract: In a semiconductor integrated circuit device and a method of designing the same, design information about circuit cells each having a desired function are described as objects according to selected purposes. The pieces of design information are registered in a cell library as cell information capable of forming any of substrate potential fixed cells and substrate potential variable cells. Further, a data sheet common to the substrate potential fixed cell and the substrate potential variable cell is offered to a user, so that the user is able to make a selection according to the user's purposes. The substrate potential fixed cells and the substrate potential variable cells are mixed together on a semiconductor chip so as to be properly used according to the functions or the like of circuit portions in which the cells are used.
    Type: Grant
    Filed: June 28, 2005
    Date of Patent: June 2, 2009
    Assignee: Renesas Technology Corp.
    Inventors: Ryuji Shibata, Shigeru Shimada
  • Publication number: 20080020498
    Abstract: To permit electrical testing of a semiconductor integrated circuit device having test pads disposed at narrow pitches probes in a pyramid or trapezoidal pyramid form are formed from metal films formed by stacking a rhodium film and a nickel film successively. Via through-holes are formed in a polyimide film between interconnects and the metal films, and the interconnects are electrically connected to the metal films. A plane pattern of one of the metal films equipped with one probe and through-hole is obtained by turning a plane pattern of the other metal film equipped with the other probe and through-hole through a predetermined angle.
    Type: Application
    Filed: September 25, 2007
    Publication date: January 24, 2008
    Inventors: Masayoshi OKAMOTO, Yoshiaki HASEGAWA, Yasuhiro MOTOYAMA, Hideyuki MATSUMOTO, Shingo YORISAKI, Akio HASEBE, Ryuji SHIBATA, Yasunori NARIZUKA, Akira YABUSHITA, Toshiyuki MAJIMA
  • Publication number: 20080013851
    Abstract: An image pickup apparatus includes: a face detection section configured to detect a face area from an image obtained by the image pickup apparatus; and a control section configured to detect at least any one of the amount of change in size of the face area detected by the face detection section and a movement speed of the face area, determine whether there is a possibility of occurrence of subject shake blur, which is blur occurring in a captured image due to the movement of a subject, on the basis of information on the detected amount of change in size of the face area or the detected movement speed of the face area, and output a warning when it is determined that there is a possibility of occurrence of subject shake blur.
    Type: Application
    Filed: July 3, 2007
    Publication date: January 17, 2008
    Applicant: SONY CORPORATION
    Inventors: Hisashi ISHIWATA, Yoshito Terashima, Tetsuo Mise, Ryuji Shibata, Masakazu Koyanagi
  • Publication number: 20050281119
    Abstract: In a semiconductor integrated circuit device and a method of designing the same, design information about circuit cells each having a desired function are described as objects according to selected purposes. The pieces of design information are registered in a cell library as cell information capable of forming any of substrate potential fixed cells and substrate potential variable cells. Further, a data sheet common to the substrate potential fixed cell and the substrate potential variable cell is offered to a user, so that the user is able to make a selection according to the user's purposes. The substrate potential fixed cells and the substrate potential variable cells are mixed together on a semiconductor chip so as to be properly used according to the functions or the like of circuit portions in which the cells are used.
    Type: Application
    Filed: June 28, 2005
    Publication date: December 22, 2005
    Inventors: Ryuji Shibata, Shigeru Shimada
  • Patent number: 6912697
    Abstract: In a semiconductor integrated circuit device and a method of designing the same, design information about circuit cells each having a desired function are described as objects according to selected purposes. The pieces of design information are registered in a cell library as cell information capable of forming any of substrate potential fixed cells and substrate potential variable cells. Further, a data sheet common to the substrate potential fixed cell and the substrate potential variable cell is offered to a user, so that the user is able to make a selection according to the user's purposes. The substrate potential fixed cells and the substrate potential variable cells are mixed together on a semiconductor chip so as to be properly used according to the functions or the like of circuit portions in which the cells are used.
    Type: Grant
    Filed: May 19, 2003
    Date of Patent: June 28, 2005
    Assignee: Renesas Technology Corp.
    Inventors: Ryuji Shibata, Shigeru Shimada
  • Publication number: 20050093565
    Abstract: To permit electrical testing of a semiconductor integrated circuit device having test pads disposed at narrow pitches probes in a pyramid or trapezoidal pyramid form are formed from metal films formed by stacking a rhodium film and a nickel film successively. Via through-holes are formed in a polyimide film between interconnects and the metal films, and the interconnects are electrically connected to the metal films. A plane pattern of one of the metal films equipped with one probe and through-hole is obtained by turning a plane pattern of the other metal film equipped with the other probe and through-hole through a predetermined angle.
    Type: Application
    Filed: October 20, 2004
    Publication date: May 5, 2005
    Inventors: Masayoshi Okamoto, Yoshiaki Hasegawa, Yasuhiro Motoyama, Hideyuki Matsumoto, Shingo Yorisaki, Akio Hasebe, Ryuji Shibata, Yasunori Narizuka, Akira Yabushita, Toshiyuki Majima
  • Publication number: 20030208725
    Abstract: In a semiconductor integrated circuit device and a method of designing the same, design information about circuit cells each having a desired function are described as objects according to selected purposes. The pieces of design information are registered in a cell library as well information capable of forming any of substrate potential fixed cells and substrate potential variable cells. Further, a data sheet common to the substrate potential fixed cell and the substrate potential variable cell is offered to a user, so that the user is able to make a selection according to the user's purposes. The substrate potential fixed cells and the substrate potential variable cells are mixed together on a semiconductor chip so as to be properly used according to the functions or the like of circuit portions in which the cells are used.
    Type: Application
    Filed: May 19, 2003
    Publication date: November 6, 2003
    Inventors: Ryuji Shibata, Shigeru Shimada
  • Patent number: 6611943
    Abstract: In a semiconductor integrated circuit device and a method of designing the same, design information about circuit cells each having a desired function are described as objects according to selected purposes. The pieces of design information are registered in a cell library as cell information capable of forming any of substrate potential fixed cells and substrate potential variable cells. Further, a data sheet common to the substrate potential fixed cell and the substrate potential variable cell is offered to a user, so that the user is able to make a selection according to the user's purposes. The substrate potential fixed cells and the substrate potential variable cells are mixed together on a semiconductor chip so as to be properly used according to the functions or the like of circuit portions in which the cells are used.
    Type: Grant
    Filed: August 28, 2001
    Date of Patent: August 26, 2003
    Assignee: Hitachi, Ltd.
    Inventors: Ryuji Shibata, Shigeru Shimada
  • Patent number: 6462978
    Abstract: In a semiconductor integrated circuit device and a method of designing the same, design information about circuit cells each having a desired function are described as objects according to selected purposes. The pieces of design information are registered in a cell library as cell information capable of forming any of substrate potential fixed cells and substrate potential variable cells. Further, a data sheet common to the substrate potential fixed cell and the substrate potential variable cell is offered to a user, so that the user is able to make a selection according to the user's purposes. The substrate potential fixed cells and the substrate potential variable cells are mixed together on a semiconductor chip so as to be properly used according to the functions or the like of circuit portions in which the cells are used.
    Type: Grant
    Filed: September 7, 2001
    Date of Patent: October 8, 2002
    Assignee: Hitachi, Ltd.
    Inventors: Ryuji Shibata, Shigeru Shimada
  • Publication number: 20020043667
    Abstract: In a semiconductor integrated circuit device and a method of designing the same, design information about circuit cells each having a desired function are described as objects according to selected purposes. The pieces of design information are registered in a cell library as cell information capable of forming any of substrate potential fixed cells and substrate potential variable cells. Further, a data sheet common to the substrate potential fixed cell and the substrate potential variable cell is offered to a user, so that the user is able to make a selection according to the user's purposes. The substrate potential fixed cells and the substrate potential variable cells are mixed together on a semiconductor chip so as to be properly used according to the functions or the like of circuit portions in which the cells are used.
    Type: Application
    Filed: August 28, 2001
    Publication date: April 18, 2002
    Inventors: Ryuji Shibata, Shigeru Shimada
  • Publication number: 20020024064
    Abstract: In a semiconductor integrated circuit device and a method of designing the same, design information about circuit cells each having a desired function are described as objects according to selected purposes. The pieces of design information are registered in a cell library as cell information capable of forming any of substrate potential fixed cells and substrate potential variable cells. Further, a data sheet common to the substrate potential fixed cell and the substrate potential variable cell is offered to a user, so that the user is able to make a selection according to the user's purposes. The substrate potential fixed cells and the substrate potential variable cells are mixed together on a semiconductor chip so as to be properly used according to the functions or the like of circuit portions in which the cells are used.
    Type: Application
    Filed: September 7, 2001
    Publication date: February 28, 2002
    Inventors: Ryuji Shibata, Shigeru Shimada
  • Patent number: 6340825
    Abstract: In a semiconductor integrated circuit device and a method of designing the same, design information about circuit cells each having a desired function are described as objects according to selected purposes. The pieces of design information are registered in a cell library as cell information capable of forming any of substrate potential fixed cells and substrate potential variable cells. Further, a data sheet common to the substrate potential fixed cell and the substrate potential variable cell is offered to a user, so that the user is able to make a selection according to the user's purposes. The substrate potential fixed cells and the substrate potential variable cells are mixed together on a semiconductor chip so as to be properly used according to the functions or the like of circuit portions in which the cells are used.
    Type: Grant
    Filed: August 7, 1998
    Date of Patent: January 22, 2002
    Assignee: Hitachi, Ltd.
    Inventors: Ryuji Shibata, Shigeru Shimada