Patents by Inventor Ryuji Tada

Ryuji Tada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6411350
    Abstract: A method for manufacturing an electrode substrate includes providing an insulating substrate and forming a first conductive layer on the insulating substrate. The first conductive layer has a narrowed wiring region and forms a first wiring pattern and a second wiring pattern. The narrowed wiring region defines a boundary region disposed between the first wiring pattern and the second wiring pattern. The method also includes forming a second conductive layer in electrical contact with the first conductive layer. The second conductive layer has a narrowed wiring region and forms a third wiring pattern and a fourth wiring pattern. The narrowed wiring region of the second conductive layer defines another boundary region disposed between the third wiring pattern and the second wiring pattern. The first and second conductive layers are formed such that the boundary regions of each of the first and second conductive layers do not overlap each other.
    Type: Grant
    Filed: February 22, 2001
    Date of Patent: June 25, 2002
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tadashi Ejiri, Ryuji Tada
  • Publication number: 20010026342
    Abstract: The present invention provides a method of manufacturing an electrode substrate. An insulating substrate is provided, on which a first conductive layer is formed. The first conductive layer has a narrowed wiring region and forms a first wiring pattern and a second wiring pattern. The narrowed wiring region defines a boundary region disposed between and separating the first wiring pattern and the second wiring pattern. A second conductive layer is formed in electrical contact with the first conductive layer. The second conductive layer has a narrowed wiring region and forms a third wiring pattern and a fourth wiring pattern. The narrowed wiring region defines another boundary region disposed between and separating the third wiring pattern and the second wiring pattern. The first and second conductive layers are formed such that the boundary regions of each of the first and second conductive layers do not overlap each other.
    Type: Application
    Filed: February 22, 2001
    Publication date: October 4, 2001
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Tadashi Ejiri, Ryuji Tada
  • Patent number: 6208390
    Abstract: An electrode substrate comprising a first conductive layer having a narrowed wiring region, defining a boundary region, separating a first wiring pattern and a second wiring pattern of the first conductive layer. The electrode substrate further comprises a second conductive layer in electrical contact with the first conductive layer, the second conductive layer having a narrowed wiring region, defining another boundary region, separating a third wiring pattern and a fourth wiring pattern of the second conductive layer.
    Type: Grant
    Filed: November 22, 1995
    Date of Patent: March 27, 2001
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tadashi Ejiri, Ryuji Tada
  • Patent number: 5784135
    Abstract: An object of the technology of our invention is to solve a luminance defect viewed as a "seam" or the like and to provide a liquid crystal display device having a screen for equally displaying an image. For example, when an exposing process is performed for one conductor layer or a dielectric layer, a total of four photomasks are used corresponding to four shot areas. A light insulation layer of a photomask used for the exposing process for patterning for example a signal line is formed so that it becomes a projection pattern of the signal line. The photomasks corresponding to adjacent shot areas are formed so that patterns of the light insulation layers of the boundary portion are engaged with each other on the plane.
    Type: Grant
    Filed: October 3, 1996
    Date of Patent: July 21, 1998
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Katsuhiko Inada, Osamu Shimada, Masahiro Seiki, Ryuji Tada, Atsushi Sugahara
  • Patent number: 5684555
    Abstract: The present invention is to provide an LCD panel in which the effective display area is great relative to the outside dimension. The LCD panel comprises an array substrate, a counter substrate and a light modulating layer obtained by injecting liquid crystal into the gap between these substrates. The array substrate includes a display area and a seal region formed around the display area. The display area includes data lines, scanning lines, switching devices controlled by the scanning lines and pixel electrodes connected to the data lines. The seal region includes a first wiring line constituted by a plurality of narrow lines and arranged along the seal line. The counter substrate has a counter electrode and is arranged opposite to the array substrate with a gap therebetween. The counter substrate is adhered to the array substrate in the seal region. A voltage is supplied to the counter electrode through the first wiring line.
    Type: Grant
    Filed: December 18, 1995
    Date of Patent: November 4, 1997
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kouichi Shiba, Ryuji Tada
  • Patent number: 5656526
    Abstract: An object of the technology of our invention is to solve a luminance defect viewed as a "seam" or the like and to provide a liquid crystal display device having a screen for equally displaying an image. For example, when an exposing process is performed for one conductor layer or a dielectric layer, a total of four photomasks are used corresponding to four shot areas. A light insulation layer of a photomask used for the exposing process for patterning for example a signal line is formed so that it becomes a projection pattern of the signal line. The photomasks corresponding to adjacent shot areas are formed so that patterns of the light insulation layers of the boundary portion are engaged with each other on the plane.
    Type: Grant
    Filed: November 7, 1995
    Date of Patent: August 12, 1997
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Katsuhiko Inada, Osamu Shimada, Masahiro Seiki, Ryuji Tada, Atsushi Sugahara