Patents by Inventor Ryuji Takishita

Ryuji Takishita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10861530
    Abstract: The purpose of the present invention is to achieve a system for solving a row hammer issue without significantly increasing a DRAM chip area. A semiconductor storage device comprises: a memory unit including a plurality of memory cells; an address latch unit that receives an active command and an address therefor, and latches and holds the address every time the active command is received; a refresh control unit that, when receiving a refresh command, instructs a memory access control unit to carry out a regular refresh operation while instructing the memory access control unit to carry out an interrupt refresh operation for an address near the address latched by the address latch unit; and the memory access control unit that carries out the regular refresh operation and the interrupt refresh operation for the memory unit on the basis of the instruction from the refresh control unit.
    Type: Grant
    Filed: April 8, 2016
    Date of Patent: December 8, 2020
    Assignee: Ultramemory Inc.
    Inventors: Yasutoshi Yamada, Ryuji Takishita
  • Publication number: 20200328184
    Abstract: The present invention provides a semiconductor module capable of improving a bandwidth between a logic chip and a RAM. According to the present invention, a semiconductor module 1 is provided with: a logic chip; a pair of RAM units 30 each composed of a lamination-type RAM module; a first interposer 10 electrically connected to the logic chip and to each of the pair of RAM units 30; and a connection unit 40 that communicatively connects the logic chip and each of the pair of RAM units 30, wherein one RAM unit 30a is placed on the first interposer 10, and has one end portion disposed so as to overlap, in the lamination direction C, one end portion of the logic chip with the connection unit 40 therebetween, and the other RAM unit 30b is disposed so as to overlap the one RAM unit 30a with the connection unit 40 therebetween, and is also disposed along the outer periphery of the logic chip.
    Type: Application
    Filed: June 26, 2020
    Publication date: October 15, 2020
    Inventors: Ryuji TAKISHITA, Takao ADACHI
  • Patent number: 10741525
    Abstract: The present invention provides a semiconductor module capable of improving a bandwidth between a logic chip and a RAM. According to the present invention, a semiconductor module 1 is provided with: a logic chip; a pair of RAM units 30 each composed of a lamination-type RAM module; a first interposer 10 electrically connected to the logic chip and to each of the pair of RAM units 30; and a connection unit 40 that communicatively connects the logic chip and each of the pair of RAM units 30, wherein one RAM unit 30a is placed on the first interposer 10, and has one end portion disposed so as to overlap, in the lamination direction C, one end portion of the logic chip with the connection unit 40 therebetween, and the other RAM unit 30b is disposed so as to overlap the one RAM unit 30a with the connection unit 40 therebetween, and is also disposed along the outer periphery of the logic chip.
    Type: Grant
    Filed: June 2, 2017
    Date of Patent: August 11, 2020
    Assignee: ULTRAMEMORY INC.
    Inventors: Ryuji Takishita, Takao Adachi
  • Publication number: 20200135696
    Abstract: The present invention provides a semiconductor module capable of improving a bandwidth between a logic chip and a RAM. According to the present invention, a semiconductor module 1 is provided with: a logic chip; a pair of RAM units 30 each composed of a lamination-type RAM module; a first interposer 10 electrically connected to the logic chip and to each of the pair of RAM units 30; and a connection unit 40 that communicatively connects the logic chip and each of the pair of RAM units 30, wherein one RAM unit 30a is placed on the first interposer 10, and has one end portion disposed so as to overlap, in the lamination direction C, one end portion of the logic chip with the connection unit 40 therebetween, and the other RAM unit 30b is disposed so as to overlap the one RAM unit 30a with the connection unit 40 therebetween, and is also disposed along the outer periphery of the logic chip.
    Type: Application
    Filed: June 2, 2017
    Publication date: April 30, 2020
    Inventors: Ryuji TAKISHITA, Takao ADACHI
  • Publication number: 20190122722
    Abstract: The purpose of the present invention is to achieve a system for solving a row hammer issue without significantly increasing a DRAM chip area. A semiconductor storage device comprises: a memory unit including a plurality of memory cells; an address latch unit that receives an active command and an address therefor, and latches and holds the address every time the active command is received; a refresh control unit that, when receiving a refresh command, instructs a memory access control unit to carry out a regular refresh operation while instructing the memory access control unit to carry out an interrupt refresh operation for an address near the address latched by the address latch unit; and the memory access control unit that carries out the regular refresh operation and the interrupt refresh operation for the memory unit on the basis of the instruction from the refresh control unit.
    Type: Application
    Filed: April 8, 2016
    Publication date: April 25, 2019
    Inventors: Yasutoshi YAMADA, Ryuji TAKISHITA
  • Patent number: 9472264
    Abstract: An apparatus includes a memory cell, a bit line coupled to the memory cell, and a sense amplifier configured to amplify a data signal on the bit line read out from the memory cell. The sense amplifier is operated in a first mode with a first power source voltage difference and operated in a second mode with a second power source voltage difference smaller than the first power source voltage difference.
    Type: Grant
    Filed: March 13, 2015
    Date of Patent: October 18, 2016
    Assignee: Micron Technology, Inc.
    Inventors: Tetsuaki Okahiro, Ryuji Takishita
  • Publication number: 20150262650
    Abstract: An apparatus includes a memory cell, a bit line coupled to the memory cell, and a sense amplifier configured to amplify a data signal on the bit line read out from the memory cell. The sense amplifier is operated in a first mode with a first power source voltage difference and operated in a second mode with a second power source voltage difference smaller than the first power source voltage difference.
    Type: Application
    Filed: March 13, 2015
    Publication date: September 17, 2015
    Inventors: TETSUAKI OKAHIRO, Ryuji Takishita
  • Patent number: 9087571
    Abstract: A semiconductor device includes an interface chip including: an internal data terminal, and a timing data storage circuit configured to output a plurality of timing set signals, and a plurality of core chips stacked with one another, each of the core chips including a plurality of memory cells, an output control circuit coupled to the timing data storage circuit of the interface chip, the output control circuit being configured to receive a corresponding one of the timing set signals and to output an output timing signal in response to the corresponding one of the timing set signals, and a data output circuit coupled to the internal data terminal of the interface chip, the data output circuit being configured to output data in response to the output timing signal, the data being derived from a corresponding one of the memory cells.
    Type: Grant
    Filed: November 1, 2013
    Date of Patent: July 21, 2015
    Assignee: PS4 Luxco S.a.r.l.
    Inventors: Hideyuki Yoko, Naohisa Nishioka, Chikara Kondo, Ryuji Takishita
  • Patent number: 9053779
    Abstract: A semiconductor device includes a first input terminal configured to receive a first clock signal, first control terminals configured to receive first control signals respectively, an output terminal, first inverters each including an input node coupled to the first input terminal, a control node coupled to a corresponding one of the first control terminals and an output node coupled to the output terminal, each of the first inverters being configured to be controlled to output an inverted first clock signal to the output terminal in response to a corresponding one of the first control signals supplied to a corresponding one of the control nodes, and an additional first inverter including an input node coupled to the first input terminal and an output node coupled to the output terminal, the additional first inverter being free from any other control nodes to output an inverted first clock signal to the output terminal.
    Type: Grant
    Filed: January 31, 2014
    Date of Patent: June 9, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Kazutaka Miyano, Ryuji Takishita, Takeshi Konno
  • Publication number: 20150116002
    Abstract: A method for comparing phases between first and second clock signal includes the first clock signals to a first precharge circuit coupled between a first node and a first terminal to which a first voltage is applied. The first clock signal is supplied to a second precharge circuit coupled between a second node and the first terminal. The second clock signal is supplied to a first discharge circuit coupled between the first node and a second terminal to which a second voltage different from the first voltage is applied. The second clock signal is supplied to a second discharge circuit coupled between the second node and the second terminal.
    Type: Application
    Filed: November 14, 2014
    Publication date: April 30, 2015
    Inventors: Koji KUROKI, Ryuji Takishita
  • Patent number: 8896348
    Abstract: In a semiconductor device, there are provided first to third pairs of nMOS transistors between a GND and two sense nodes and first to third pairs of pMOS transistors between the two sense nodes and the power supply. A first internal clock signal and its inverted signal are supplied to gates of the first pair of nMOS transistors and the second pair of nMOS transistors, respectively. Complementary external clock signals are supplied to the gates of the third pairs of nMOS transistors and the third pairs of pMOS transistors. An inverted version of a second internal clock signal and the second internal clock signal are supplied to gates of the first and second pairs of pMOS transistors. The two sense nodes are connected to inputs of a differential amplifier. The output of the differential amplifier is latched by a latch circuit. An equalizing circuit precharges/equalizes the two sense nodes.
    Type: Grant
    Filed: November 22, 2013
    Date of Patent: November 25, 2014
    Assignee: PS4 Luxco S.a.r.l.
    Inventors: Koji Kuroki, Ryuji Takishita
  • Publication number: 20140344612
    Abstract: To provide a semiconductor device including an interface chip and a core chip and a measurement-target signal line and a reference signal line each including a through silicon via provided in the core chip and electrically connecting the interface chip and the core chip. The interface chip outputs a test clock generated by a first signal generation circuit to the core chip. The core chip includes a second signal generation circuit that generates a predetermined measurement signal from the test clock, and outputs the predetermined measurement signal to the measurement-target signal line and the reference signal line in a simultaneous manner. Further, the interface chip detects a phase difference of a plurality of predetermined measurement signals input via the measurement-target signal line and the reference signal line by an operational amplifier, and outputs a test result to a determination circuit. 1.
    Type: Application
    Filed: August 5, 2014
    Publication date: November 20, 2014
    Inventors: Hideyuki YOKO, Kentaro Hara, Ryuji Takishita
  • Publication number: 20140232438
    Abstract: A semiconductor device includes a first input terminal configured to receive a first clock signal, first control terminals configured to receive first control signals respectively, an output terminal, first inverters each including an input node coupled to the first input terminal, a control node coupled to a corresponding one of the first control terminals and an output node coupled to the output terminal, each of the first inverters being configured to be controlled to output an inverted first clock signal to the output terminal in response to a corresponding one of the first control signals supplied to a corresponding one of the control nodes, and an additional first inverter including an input node coupled to the first input terminal and an output node coupled to the output terminal, the additional first inverter being free from any other control nodes to output an inverted first clock signal to the output terminal.
    Type: Application
    Filed: January 31, 2014
    Publication date: August 21, 2014
    Applicant: ELPIDA MEMORY, INC.
    Inventors: Kazutaka Miyano, Ryuji Takishita, Takeshi Konno
  • Patent number: 8803545
    Abstract: To provide a semiconductor device including an interface chip and a core chip and a measurement-target signal line and a reference signal line each including a through silicon via provided in the core chip and electrically connecting the interface chip and the core chip. The interface chip outputs a test clock generated by a first signal generation circuit to the core chip. The core chip includes a second signal generation circuit that generates a predetermined measurement signal from the test clock, and outputs the predetermined measurement signal to the measurement-target signal line and the reference signal line in a simultaneous manner. Further, the interface chip detects a phase difference of a plurality of predetermined measurement signals input via the measurement-target signal line and the reference signal line by an operational amplifier, and outputs a test result to a determination circuit.
    Type: Grant
    Filed: January 14, 2011
    Date of Patent: August 12, 2014
    Assignee: PS4 Luxco S.A.R.L.
    Inventors: Hideyuki Yoko, Kentaro Hara, Ryuji Takishita
  • Publication number: 20140132316
    Abstract: In a semiconductor device, there are provided first to third pairs of nMOS transistors between a GND and two sense nodes and first to third pairs of pMOS transistors between the two sense nodes and the power supply. A first internal clock signal and its inverted signal are supplied to gates of the first pair of nMOS transistors and the second pair of nMOS transistors, respectively. Complementary external clock signals are supplied to the gates of the third pairs of nMOS transistors and the third pairs of pMOS transistors. An inverted version of a second internal clock signal and the second internal clock signal are supplied to gates of the first and second pairs of pMOS transistors. The two sense nodes are connected to inputs of a differential amplifier. The output of the differential amplifier is latched by a latch circuit. An equalizing circuit precharges/equalizes the two sense nodes.
    Type: Application
    Filed: November 22, 2013
    Publication date: May 15, 2014
    Applicant: Elpida Memory, Inc.
    Inventors: Koji Kuroki, Ryuji Takishita
  • Publication number: 20140056086
    Abstract: A semiconductor device includes an interface chip including: an internal data terminal, and a timing data storage circuit configured to output a plurality of timing set signals, and a plurality of core chips stacked with one another, each of the core chips including a plurality of memory cells, an output control circuit coupled to the timing data storage circuit of the interface chip, the output control circuit being configured to receive a corresponding one of the timing set signals and to output an output timing signal in response to the corresponding one of the timing set signals, and a data output circuit coupled to the internal data terminal of the interface chip, the data output circuit being configured to output data in response to the output timing signal, the data being derived from a corresponding one of the memory cells.
    Type: Application
    Filed: November 1, 2013
    Publication date: February 27, 2014
    Applicant: ELPIDA MEMORY, INC.
    Inventors: Hideyuki Yoko, Naohisa Nishioka, Chikara Kondo, Ryuji Takishita
  • Patent number: 8604835
    Abstract: In a semiconductor device, there are provided first to third pairs of nMOS transistors between a GND and two sense nodes and first to third pairs of pMOS transistors between the two sense nodes and the power supply. A first internal clock signal and its inverted signal are supplied to gates of the first pair of nMOS transistors and the second pair of nMOS transistors, respectively. Complementary external clock signals are supplied to the gates of the third pairs of nMOS transistors and the third pairs of pMOS transistors. An inverted version of a second internal clock signal and the second internal clock signal are supplied to gates of the first and second pairs of pMOS transistors. The two sense nodes are connected to inputs of a differential amplifier. The output of the differential amplifier is latched by a latch circuit. Also provided an equalizing circuit precharging/equalizing the two sense nodes (FIG. 2).
    Type: Grant
    Filed: August 30, 2010
    Date of Patent: December 10, 2013
    Assignee: Elpida Memory, Inc.
    Inventors: Koji Kuroki, Ryuji Takishita
  • Patent number: 8599641
    Abstract: Each of the core chips includes a data output circuit that outputs read data to the interface chip in response to a read command, and an output timing adjustment circuit that equalizes the periods of time required between the reception of the read command and the outputting of the read data from the data output circuit among the core chips. With this arrangement, a sufficient latch margin for read data to be input can be secured on the interface chip side. Furthermore, as the output timing is adjusted on each core chip side, there is no need to prepare the same number of latch timing control circuits as the number of core chips on the interface chip side.
    Type: Grant
    Filed: October 7, 2010
    Date of Patent: December 3, 2013
    Assignee: Elpida Memory, Inc.
    Inventors: Hideyuki Yoko, Naohisa Nishioka, Chikara Kondo, Ryuji Takishita
  • Patent number: 8310382
    Abstract: In a stacked semiconductor device in which a plurality of through silicon vias used for data transfer are shared among a plurality of semiconductor chips, a first semiconductor chip included in the semiconductor chips holds through silicon via switching information for specifying a through silicon via among the through silicon vias to be used for data transfer, and transfers the through silicon via switching information to a second semiconductor chip included in the semiconductor chips. According to the present invention, because the through silicon via switching information is transferred from the first semiconductor chip to the second semiconductor chip, a circuit for storing the through silicon via switching information in a nonvolatile manner is not required in the second semiconductor chip. With this arrangement, a chip area of the second semiconductor chip can be reduced.
    Type: Grant
    Filed: October 8, 2010
    Date of Patent: November 13, 2012
    Assignee: Elpida Memory, Inc.
    Inventors: Akira Ide, Ryuji Takishita
  • Publication number: 20110175639
    Abstract: To provide a semiconductor device including an interface chip and a core chip and a measurement-target signal line and a reference signal line each including a through silicon via provided in the core chip and electrically connecting the interface chip and the core chip. The interface chip outputs a test clock generated by a first signal generation circuit to the core chip. The core chip includes a second signal generation circuit that generates a predetermined measurement signal from the test clock, and outputs the predetermined measurement signal to the measurement-target signal line and the reference signal line in a simultaneous manner. Further, the interface chip detects a phase difference of a plurality of predetermined measurement signals input via the measurement-target signal line and the reference signal line by an operational amplifier, and outputs a test result to a determination circuit.
    Type: Application
    Filed: January 14, 2011
    Publication date: July 21, 2011
    Applicant: Elpida Memory, Inc.
    Inventors: Hideyuki Yoko, Kentaro Hara, Ryuji Takishita