Abstract: A method for programming a non-volatile memory structure, comprises initiating a two-dimensional fractional number of bits-per-cell programming scheme of a plurality of memory cells, wherein the memory structure comprises: (1) a first memory array comprising a first population of memory cells and the associated peripheral circuitry disposed below the first population of cells, (2) a second memory array positioned above the first memory array and comprising a second population of memory cells and associated peripheral circuitry disposed above the second population of cells, and (3) a data bus tap electrically coupling the first and second memory arrays. Further, the method comprises: (1) storing input data in data latches associated with the first array and with the second array. Additionally, the method comprises converting the stored data using data conversion logic implemented by a data path circuit of the first and second arrays and rewriting the converted data to the latches.

Abstract: A method for programming a non-volatile memory structure, comprises initiating a two-dimensional fractional number of bits-per-cell programming scheme of a plurality of memory cells, wherein the memory structure comprises: (1) a first memory array comprising a first population of memory cells and the associated peripheral circuitry disposed below the first population of cells, (2) a second memory array positioned above the first memory array and comprising a second population of memory cells and associated peripheral circuitry disposed above the second population of cells, and (3) a data bus tap electrically coupling the first and second memory arrays. Further, the method comprises: (1) storing input data in data latches associated with the first array and with the second array. Additionally, the method comprises converting the stored data using data conversion logic implemented by a data path circuit of the first and second arrays and rewriting the converted data to the latches.

Abstract: A method for programming a non-volatile memory structure, wherein the method comprises initiating a two-dimensional fractional number of bits-per-cell programming scheme with respect to at least a first memory cell and a second memory cell of a plurality of memory cells of the memory structure, wherein the memory structure comprises: (1) a first memory array that comprises a first population of the plurality of memory cells and associated peripheral circuitry disposed below the first population of the plurality of memory cells, (2) a second memory array that is positioned above the first memory array and comprises a second population of the plurality of memory cells and the associated peripheral circuitry that is disposed above the second population of the plurality of memory cells, and (3) a data bus tap electrically coupling the first memory array and the second memory array.

Abstract: A method for performing a read operation of a memory block of a read-only memory array, wherein the method comprises first enabling bit line precharge circuitry of the memory block, (thereby precharging one or more bit lines of the memory block to a first voltage level), enabling a word line of one or more addressed memory cells of the memory block, enabling a leakage current reduction circuit of the memory block, thereby generating across the addressed memory cells a first voltage differential equal to the first voltage level; subsequently discharging the addressed memory cells; disabling the word line of the one or more addressed memory cells; disabling the bit line precharge circuitry; and disabling the leakage current reduction circuit, thereby generating across the one or more addressed memory cells a second voltage differential that is equal to less than the first voltage differential.

Abstract: A method for performing a read operation of a memory block of a read-only memory array, wherein the method comprises first enabling bit line precharge circuitry of the memory block, (thereby precharging one or more bit lines of the memory block to a first voltage level), enabling a word line of one or more addressed memory cells of the memory block, enabling a leakage current reduction circuit of the memory block, thereby generating across the addressed memory cells a first voltage differential equal to the first voltage level; subsequently discharging the addressed memory cells; disabling the word line of the one or more addressed memory cells; disabling the bit line precharge circuitry; and disabling the leakage current reduction circuit, thereby generating across the one or more addressed memory cells a second voltage differential that is equal to less than the first voltage differential.

Abstract: A temperature sensor circuit has a reference voltage generator that is trimmable at two temperatures for increased accuracy. The reference voltage generation section generates a reference voltage, the level of which is trimmable. A voltage divider section is connected to receive the reference voltage from the reference voltage generation section and generate a plurality of comparison voltage levels determined by the reference voltage and a trimmable resistance. An analog-to-digital converter can then be connected to a temperature dependent voltage section to receive the temperature dependent output voltage, such as a proportional to absolute temperature type (PTAT) behavior, and connected to the voltage divider section to receive the comparison voltage levels. The analog to digital converter generates an output indicative of the temperature based upon a comparison of the temperature dependent output voltage to the comparison voltage levels.

Abstract: A temperature sensor circuit has a reference voltage generator that is trimmable at two temperatures for increased accuracy. The reference voltage generation section generates a reference voltage, the level of which is trimmable. A voltage divider section is connected to receive the reference voltage from the reference voltage generation section and generate a plurality of comparison voltage levels determined by the reference voltage and a trimmable resistance. An analog-to-digital converter can then be connected to a temperature dependent voltage section to receive the temperature dependent output voltage, such as a proportional to absolute temperature type (PTAT) behavior, and connected to the voltage divider section to receive the comparison voltage levels. The analog to digital converter generates an output indicative of the temperature based upon a comparison of the temperature dependent output voltage to the comparison voltage levels.

Abstract: A temperature sensor circuit has a reference voltage generator that is trimmable at two temperatures for increased accuracy. The reference voltage generation section generates a reference voltage, the level of which is trimmable. A voltage divider section is connected to receive the reference voltage from the reference voltage generation section and generate a plurality of comparison voltage levels determined by the reference voltage and a trimmable resistance. An analog-to-digital converter can then be connected to a temperature dependent voltage section to receive the temperature dependent output voltage, such as a proportional to absolute temperature type (PTAT) behavior, and connected to the voltage divider section to receive the comparison voltage levels. The analog to digital converter generates an output indicative of the temperature based upon a comparison of the temperature dependent output voltage to the comparison voltage levels.

Abstract: A temperature sensor circuit has a reference voltage generator that is trimmable at two temperatures for increased accuracy. The reference voltage generation section generates a reference voltage, the level of which is trimmable. A voltage divider section is connected to receive the reference voltage from the reference voltage generation section and generate a plurality of comparison voltage levels determined by the reference voltage and a trimmable resistance. An analog-to-digital converter can then be connected to a temperature dependent voltage section to receive the temperature dependent output voltage, such as a proportional to absolute temperature type (PTAT) behavior, and connected to the voltage divider section to receive the comparison voltage levels. The analog to digital converter generates an output indicative of the temperature based upon a comparison of the temperature dependent output voltage to the comparison voltage levels.

Abstract: A mechanism for tilting an outboard motor. The mechanism has an outboard motor which is attached to a hull so as to be tilted up and down, a cylinder for driving the outboard motor to change a posture of the outboard motor, and a linkage to connect the outboard motor and a rod of the cylinder. The cylinder itself serves as a central shaft, around which the outboard motor is tilted up and down. Since the cylinder has a single-walled construction, the mechanism of the present invention is simple and can be economically manufactured.