Abstract: A field-effect transistor includes a silicon layer formed on an insulating film, a first-conductivity-type base and a second-conductivity-type source layers formed in the silicon layer being adjacent to each other, a second-conductivity-type drain layer formed in the silicon layer being separated from the source layer with the base layer being interposed therebetween, a gate-to-drain offset layer formed between the base and drain layers, having a resistance higher than that of the base layer, and a gate electrode formed on at least a surface of the base layer via a gate insulating film wherein the silicon layer in which the base layer is formed is a strained silicon layer.

Abstract: Power MISFET 20 includes SIO substrate 4 composed of first silicon substrate 1, BOX layer 2 formed on the front surface of first silicon substrate 1 and silicon substrate 3 formed on BOX layer 2. Second silicon substrate 3 is provided with lightly doped-impurity offset layer 5, P layer 6, N+ source layer 7, and N+ drain layer 8. First gate electrode 10 made of poly crystalline silicon is formed on Player 6 through gate insulation film 9. Second gate electrode 15 is formed on the back surface of first silicon substrate 1 while BOX layer 2 functions as a gate insulation film.

Abstract: According to the present invention, there is provided a field-effect transistor comprising: a silicon layer formed on an insulating film; a first-conductivity-type base layer formed in said silicon layer; a second-conductivity-type source layer formed in said silicon layer so as to be adjacent to said first-conductivity-type base layer; a second-conductivity-type drain layer formed in said silicon layer so as to be separated from said second-conductivity-type source layer with said first-conductivity-type base layer being interposed therebetween; a gate-to-drain offset layer formed between said first-conductivity-type base layer and said second-conductivity-type drain layer in said silicon layer, and having a resistance higher than that of said first-conductivity-type base layer; and a gate electrode formed on at least a surface of said first-conductivity-type base layer via a gate insulating film, wherein said silicon layer in which said first-conductivity-type base layer is formed is a strained silicon laye