Abstract: A method of forming a pattern is provided. The method includes an etching step of forming a predetermined pattern in a silicon-containing film by etching the silicon-containing film deposited on a substrate through a mask by plasma generated from an etching gas containing a fluorocarbon gas, and a film deposition step of depositing a silicon oxide film or a silicon nitride film on a surface of the predetermined pattern by oxidizing or nitriding a silicon-containing layer adsorbed on the surface of the predetermined pattern by supplying a silicon compound gas, by using plasma generated from an oxidation gas or a nitriding gas.

Abstract: A method of forming a pattern is provided. The method includes an etching step of forming a predetermined pattern in a silicon-containing film by etching the silicon-containing film deposited on a substrate through a mask by plasma generated from an etching gas containing a fluorocarbon gas, and a film deposition step of depositing a silicon oxide film or a silicon nitride film on a surface of the predetermined pattern by oxidizing or nitriding a silicon-containing layer adsorbed on the surface of the predetermined pattern by supplying a silicon compound gas, by using plasma generated from an oxidation gas or a nitriding gas.

Abstract: The invention provides a systems and methods for creating Double Pattern (DP) structures on a patterned wafer in real-time using Dual Pattern Contact-Etch (DPCE) processing sequences and associated Contact-Etch-Multi-Input/Multi-Output (CE-MIMO) models. The DPCE processing sequences can include one or more contact-etch procedures, one or more measurement procedures, one or more contact-etch modeling procedures, and one or more contact-etch verification procedures. The CE-MIMO model uses dynamically interacting behavioral modeling between multiple layers and/or multiple contact-etch procedures. The multiple layers and/or the multiple contact-etch procedures can be associated with the creation of lines, trenches, vias, spacers, contacts, and gate structures that can be created during Double Patterning (DP) procedures.

Abstract: The invention provides a systems and methods for creating Double Pattern (DP) structures on a patterned wafer in real-time using Dual Pattern Contact-Etch (DPCE) processing sequences and associated Contact-Etch-Multi-Input/Multi-Output (CE-MIMO) models. The DPCE processing sequences can include one or more contact-etch procedures, one or more measurement procedures, one or more contact-etch modeling procedures, and one or more contact-etch verification procedures. The CE-MIMO model uses dynamically interacting behavioral modeling between multiple layers and/or multiple contact-etch procedures. The multiple layers and/or the multiple contact-etch procedures can be associated with the creation of lines, trenches, vias, spacers, contacts, and gate structures that can be created during Double Patterning (DP) procedures.

Abstract: Disclosed is a semiconductor device fabricating method. A substrate is provided thereon with: an inorganic insulating film; a first inorganic sacrifice film stacked on the inorganic insulating film and having components different from those of the inorganic insulating film; a second sacrifice film formed of an inorganic insulative film stacked on the first sacrifice film, wherein a pattern for forming grooves for wiring embedment is formed in the second sacrifice film; and an organic layer including a photoresist film, wherein a pattern for forming holes for wiring embedment is formed in the organic film. According to the present invention, the thickness of the organic layer is set to be greater than the sum of the thicknesses of etch target films, i.e., the insulating film, the first sacrifice film and the second sacrifice film; the etch target films are etched in a selectivity-less manner by using plasma generated from a mixed gas of CF4 gas and CHF3 gas.

Abstract: To provide a manufacturing method for semiconductor manufacturing device that can suppress the development of striations when forming holes by etching an etch target film composed of an inorganic insulating film, a first sacrifice film stacked on this insulating film and having components different from those of the insulating film, a second sacrifice film formed of an inorganic insulating film, whereon a pattern for forming grooves for wiring embedment on the insulating film is formed. In a substrate including a photoresist film, wherein a pattern for forming holes for embedding the wiring material on the upper layer of the above etch target film, a thickness of the above organic layer is greater than a thickness of an etch target layer composed of the above insulating film, the above first sacrifice film and the above second sacrifice film, a mixed gas containing CF4 gas and CHF3 gas is converted into plasma, and the etch target layer is etched by using the plasma.