Abstract: An annular type gas turbine combustor having a plurality of fuel nozzle assemblies (10) on a circumference includes a pilot nozzle unit (12) for spraying a fuel for diffusive combustion from a pilot outer peripheral nozzle (34) into a combustion chamber (8), a main nozzle unit (14) provided so as to surround the pilot nozzle unit (12) for spraying a fuel for premix combustion, and a flow guide (27) disposed on a downstream side of each of the fuel nozzle assemblies (10) and having a sectional area of a passage for air and air-fuel mixture from each of the fuel nozzle assemblies (10), which gradually increase in a downstream direction.

Abstract: A fuel injector includes a pilot fuel injector, configured to inject the fuel into a combustion chamber, and a main fuel injector provided coaxially with the pilot fuel injector so as to surround the pilot fuel injector and configured to have a main flow path to generate a premixed air-fuel mixture. The main flow path includes an outer main air passage located radially outwardly and configured to supply a compressed air in an axial direction into an annular premixed air-fuel mixture passage, an inner main air passage located radially inwardly and configured to supply the compressed air into the premixed air-fuel mixture passage from a radially inner side. The injector further includes a main fuel injection port to inject the fuel from an axially upstream side into the inner main air passage.

Abstract: A gas turbine combustor 1 of the present invention comprises a fuel injector 13 for injecting a fuel F toward a combustion chamber 11; a swirler 14 which takes-in compressed air CA generated in a compressor and swirl the compressed air CA, in the vicinity of the fuel injector 13; a tubular guide member 34 for guiding the compressed air CA taken-in from the swirler 14, to the combustion chamber 11; and a heat shield 23 having a cylindrical portion 23b located outward relative to the guide member 34; wherein the cylindrical portion 23b has a purge hole 40; and air is introduced through the purge hole 40 and is supplied to a space 39 formed between the guide member 34 and the cylindrical portion 23b.

Abstract: A fuel injector includes: a pilot injector configured to spray fuel so as to form a first combustion region in a combustion chamber; and a main injector provided coaxially with the pilot injector so as to surround the pilot injector and configured to supply a fuel-air mixture that is a mixture of the fuel and air to form a second combustion region in the combustion chamber, wherein the main injector includes: a first inflow channel through which the air having a major flow component in an axial direction is taken; a second inflow channel through which the air having a major flow component in a radial direction is taken and which causes the air therein to meet the air from the first inflow channel; and a main fuel injecting portion configured to inject the fuel only to the second inflow channel.

Abstract: A fuel injector includes: a pilot injector configured to spray fuel so as to form a first combustion region in a combustion chamber; and a main injector provided coaxially with the pilot injector so as to surround the pilot injector and configured to supply a fuel-air mixture that is a mixture of the fuel and air to form a second combustion region in the combustion chamber, wherein the pilot injector includes: a center nozzle configured to eject air jet flowing straight in an axial direction on a central axis of the pilot injector; an inside swirler provided on a radially outer side of the center nozzle and configured to cause inflow air to swirl around the central axis; and a pilot fuel injecting portion configured to inject the fuel from between the center nozzle and the inside swirler to air flow in the center nozzle.

Abstract: A memory cell unit including: a semiconductor substrate having a source diffusion layer in at least a part of a surface thereof; a column-shaped semiconductor layer provided on the semiconductor substrate, and having a drain diffusion layer provided in an uppermost portion thereof and a first low concentration impurity diffusion layer provided in an entire bottom portion thereof; a memory cell arrangement which includes a plurality of memory cells provided in a peripheral wall of the column-shaped semiconductor layer and connected in series perpendicularly to the substrate, the memory cells each having a charge storage layer and a control gate; a second impurity diffusion layer provided at a lower end of the memory cell arrangement; and a selection transistor having a gate electrode provided around the peripheral wall of the column-shaped semiconductor layer and connecting the second impurity diffusion layer and the first impurity diffusion layer; wherein the first impurity diffusion layer extends into a part

Abstract: A nonvolatile semiconductor storage device including: a plurality of memory cell unit groups each comprising one or more NAND nonvolatile memory cell units each comprising at least one memory cell having a control gate, a first selection transistor having a first selection gate, and a second selection transistor having a second selection gate, the memory cell unit groups each further comprising a control gate line connected to the control gate, a first selection gate line connected to the first selection gate, and a second selection gate line connected to the second selection gate; a common control gate line connected commonly to the control gate lines of different ones of the memory cell unit groups; a first common selection gate line connected commonly to the first selection gate lines of different ones of the memory cell unit groups; and a second common selection gate line connected commonly to the second selection gate lines of different ones of the memory cell unit groups; wherein the memory cells in the

Abstract: A method for driving a nonvolatile memory device including a semiconductor substrate, an island semiconductor layer on the substrate, a memory cell having a control gate and a charge storage layer surrounding a peripheral surface of the island semiconductor layer, a first selection transistor provided between the memory cell and the substrate and having a first selection gate, a source diffusion layer between the substrate and the island semiconductor layer, a drain diffusion layer provided in an opposing end of the island semiconductor layer from the source diffusion layer, and a second selection transistor provided between the memory cell and the drain diffusion layer and having a second selection gate, the method comprising the steps of: applying a negative first voltage to the drain and the first selection gate, applying a positive second voltage to the second selection gate, and applying 0V or a positive third voltage to the source; and applying a positive fourth voltage higher than the second voltage to

Abstract: A memory cell unit including: a semiconductor substrate having a source diffusion layer in at least a part of a surface thereof; a column-shaped semiconductor layer provided on the semiconductor substrate, and having a drain diffusion layer provided in an uppermost portion thereof and a first low concentration impurity diffusion layer provided in an entire bottom portion thereof; a memory cell arrangement which includes a plurality of memory cells provided in a peripheral wall of the column-shaped semiconductor layer and connected in series perpendicularly to the substrate, the memory cells each having a charge storage layer and a control gate; a second impurity diffusion layer provided at a lower end of the memory cell arrangement; and a selection transistor having a gate electrode provided around the peripheral wall of the column-shaped semiconductor layer and connecting the second impurity diffusion layer and the first impurity diffusion layer; wherein the first impurity diffusion layer extends into a part

Abstract: A nonvolatile semiconductor storage device including: a plurality of memory cell unit groups each comprising one or more NAND nonvolatile memory cell units each comprising at least one memory cell having a control gate, a first selection transistor having a first selection gate, and a second selection transistor having a second selection gate, the memory cell unit groups each further comprising a control gate line connected to the control gate, a first selection gate line connected to the first selection gate, and a second selection gate line connected to the second selection gate; a common control gate line connected commonly to the control gate lines of different ones of the memory cell unit groups; a first common selection gate line connected commonly to the first selection gate lines of different ones of the memory cell unit groups; and a second common selection gate line connected commonly to the second selection gate lines of different ones of the memory cell unit groups; wherein the memory cells in the

Abstract: A method for driving a nonvolatile memory device including a semiconductor substrate, an island semiconductor layer on the substrate, a memory cell having a control gate and a charge storage layer surrounding a peripheral surface of the island semiconductor layer, a first selection transistor provided between the memory cell and the substrate and having a first selection gate, a source diffusion layer between the substrate and the island semiconductor layer, a drain diffusion layer provided in an opposing end of the island semiconductor layer from the source diffusion layer, and a second selection transistor provided between the memory cell and the drain diffusion layer and having a second selection gate, the method comprising the steps of: applying a negative first voltage to the drain and the first selection gate, applying a positive second voltage to the second selection gate, and applying 0V or a positive third voltage to the source; and applying a positive fourth voltage higher than the second voltage to