Patents by Inventor Ryusuke Murakami

Ryusuke Murakami has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9547475
    Abstract: According to one embodiment, a random number generating circuit includes first to N-th oscillating circuits (N is a natural number equal to 2 or greater), first to N-th latch circuits that latch outputs of the first to N-th oscillating circuits by a first clock having a first frequency, first to N-th exclusive OR circuits, (N+1)-th to (2×N)-th latch circuits that latch outputs of the first to N-th exclusive OR circuits by the first clock, an (N+1)-th exclusive OR circuit that outputs an exclusive OR of outputs of the (N+1)-th to (2×N)-th latch circuits, and an M-bit shift register that converts serial data output from the (N+1)-th exclusive OR circuit into M-bit parallel data (M is a natural number equal to 2 or greater) by a second clock having a second frequency.
    Type: Grant
    Filed: November 21, 2013
    Date of Patent: January 17, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shinichi Yasuda, Tetsufumi Tanamoto, Noriko Inoue, Akira Tomita, Ryusuke Murakami, Atsushi Shimbo
  • Publication number: 20140143292
    Abstract: According to one embodiment, a random number generating circuit includes first to N-th oscillating circuits (N is a natural number equal to 2 or greater), first to N-th latch circuits that latch outputs of the first to N-th oscillating circuits by a first clock having a first frequency, first to N-th exclusive OR circuits, (N+1)-th to (2×N)-th latch circuits that latch outputs of the first to N-th exclusive OR circuits by the first clock, an (N+1)-th exclusive OR circuit that outputs an exclusive OR of outputs of the (N+1)-th to (2×N)-th latch circuits, and an M-bit shift register that converts serial data output from the (N+1)-th exclusive OR circuit into M-bit parallel data (M is a natural number equal to 2 or greater) by a second clock having a second frequency.
    Type: Application
    Filed: November 21, 2013
    Publication date: May 22, 2014
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Shinichi YASUDA, Tetsufumi Tanamoto, Noriko Inoue, Akira Tomita, Ryusuke Murakami, Atsushi Shimbo
  • Patent number: 5802210
    Abstract: An image processing system conducts a video effect processing. In the mosaic-image-processing, a dc component of inversely quantized discrete cosine transform (DCT) coefficients is multiplied by a constant h other than zero and an ac component of the inversely quantized DCT coefficients is replaced with zero. In the case of monochromatic-image-processing, a dc component D.sub.y of a luminance block Y of the inversely quantized DCT coefficients is multiplied by a constant i other than zero and an ac component A.sub.y of the luminance block Y is multiplied by a constant I other than zero, dc components D.sub.Cb and D.sub.Cr of chrominance blocks Cb and Cr of the inversely quantized DCT coefficients are replaced with constants j and k, respectively, and ac components A.sub.Cb and A.sub.Cr of the chrominance blocks Cb and Cr are replaced with constants J and K, respectively. In the thermographic-image processing, a dc component D.sub.y of the luminance block Y is processed into dc components D.sub.Cb '=mD.sub.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: September 1, 1998
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masanori Kurata, Ryusuke Murakami, Yusei Itaya