Patents by Inventor Ryusuke Nakasaki

Ryusuke Nakasaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9558873
    Abstract: A method for manufacturing a superconducting wire material in which the superconducting current is not saturated even when a superconducting layer is made into a thick film, and a superconducting wire material. In the method a superconducting layer is formed on a metal substrate interposed by an intermediate layer, the method including heating the metal substrate up to the film-formation temperature of a superconducting film for forming the superconducting layer, forming a superconducting film having a film thickness of at least 10 nm and no more than 200 nm on the intermediate layer, and reducing the metal substrate temperature to a level below the film-formation temperature of the superconducting film, and the superconducting film-formation, including the heating, the film-formation, and the cooling, are performed a plurality of times.
    Type: Grant
    Filed: February 1, 2012
    Date of Patent: January 31, 2017
    Assignees: FURUKAWA ELECTRIC CO., LTD., CHUBU ELECTRIC POWER COMPANY, INCORPORATED
    Inventors: Ryusuke Nakasaki, Akinobu Nakai, Tomonori Watanabe, Naoji Kashima, Shigeo Nagaya
  • Publication number: 20150005175
    Abstract: A method for manufacturing a superconducting wire material in which the superconducting current is not saturated even when a superconducting layer is made into a thick film, and a superconducting wire material. In the method a superconducting layer is formed on a metal substrate interposed by an intermediate layer, the method including heating the metal substrate up to the film-formation temperature of a superconducting film for forming the superconducting layer, forming a superconducting film having a film thickness of at least 10 nm and no more than 200 nm on the intermediate layer, and reducing the metal substrate temperature to a level below the film-formation temperature of the superconducting film, and the superconducting film-formation, including the heating, the film-formation, and the cooling, are performed a plurality of times.
    Type: Application
    Filed: February 1, 2012
    Publication date: January 1, 2015
    Applicants: FURUKAWA ELECTRIC CO., LTD., CHUBU ELECTRIC POWER COMPANY, INCORPORATED
    Inventors: Ryusuke Nakasaki, Akinobu Nakai, Tomonori Watanabe, Naoji Kashima, Shigeo Nagaya
  • Publication number: 20120180725
    Abstract: A cold wall type CVD apparatus that can enhance a raw material yield is provided. The CVD apparatus has a raw material gas jetting unit 11 for jetting raw material gas, a susceptor 14 for supporting a tape-shaped base material T and heating the tape-shaped base material T through heat transfer, a heater 15 for heating the susceptor 14, an inert gas introducing unit 12a for introducing inert gas to suppress the contact between the heater and the raw material gas, and a raw material gas transport passage LG for guiding the raw material gas jetted from the raw material gas jetting unit 11 to the surface of the tape-shaped base material.
    Type: Application
    Filed: January 17, 2012
    Publication date: July 19, 2012
    Applicant: FURUKAWA ELECTRIC CO., LTD.
    Inventors: Shinya Yasunaga, Masakiyo Ikeda, Hiroshi KIKUCHI, Noriyasu Sakurai, Ryusuke Nakasaki, Jin Liu, Satoshi Yamano
  • Patent number: 6911713
    Abstract: An EA-DFB module including a DFB laser diode and an EA modulator formed on an InP first-conductivity-type substrate has a mesa stripe, a current blocking structure formed on both side surfaces of the mesa strip and a second InP cladding layer formed on top of the mesa stripe and the current blocking structure. The current blocking structure includes a Fe-doped semi-insulating film, a first conductivity-type buried layer and a carrier-depleted layer. The carrier-depleted layer reduces the parasitic capacitance at the boundary between the first-conductivity-type buried layer and the second InP cladding layer.
    Type: Grant
    Filed: July 14, 2003
    Date of Patent: June 28, 2005
    Assignee: The Furukawa Electric Co., Ltd.
    Inventors: Nariaki Ikeda, Takeharu Yamaguchi, Satoshi Arakawa, Nobumitsu Yamanaka, Akihiko Kasukawa, Ryusuke Nakasaki
  • Publication number: 20040048406
    Abstract: An EA-DFB module including a DFB laser diode and an EA modulator formed on an InP first-conductivity-type substrate has a mesa stripe, a current blocking structure formed on both side surfaces of the mesa strip and a second InP cladding layer formed on top of the mesa stripe and the current blocking structure. The current blocking structure includes a Fe-doped semi-insulating film, a first conductivity-type buried layer and a carrier-depleted layer. The carrier-depleted layer reduces the parasitic capacitance at the boundary between the first-conductivity-type buried layer and the second InP cladding layer.
    Type: Application
    Filed: July 14, 2003
    Publication date: March 11, 2004
    Applicant: THE FURUKAWA ELECTRIC CO., LTD.
    Inventors: Nariaki Ikeda, Takeharu Yamaguchi, Satoshi Arakawa, Nobumitsu Yamanaka, Akihiko Kasukawa, Ryusuke Nakasaki