Patents by Inventor Ryusuke Obara

Ryusuke Obara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor integrated circuit
    Patent number: 9882571
    Abstract: A semiconductor integrated circuit includes: a phase locked loop circuit which outputs a clock signal; an internal circuit which executes processing; a capacitor; and a switch circuit which connects the capacitor to either of the phase locked loop circuit and the internal circuit.
    Type: Grant
    Filed: April 20, 2016
    Date of Patent: January 30, 2018
    Assignee: SOCIONEXT INC.
    Inventors: Hiroyuki Homma, Kenichi Nomura, Ryusuke Obara
  • SEMICONDUCTOR INTEGRATED CIRCUIT
    Publication number: 20160233868
    Abstract: A semiconductor integrated circuit includes: a phase locked loop circuit which outputs a clock signal; an internal circuit which executes processing; a capacitor; and a switch circuit which connects the capacitor to either of the phase locked loop circuit and the internal circuit.
    Type: Application
    Filed: April 20, 2016
    Publication date: August 11, 2016
    Inventors: Hiroyuki HOMMA, Kenichi NOMURA, Ryusuke OBARA
  • Delay control circuit
    Patent number: 7525364
    Abstract: A first variable delay circuit delays an input signal, introduces a first delay into a first edge of the input signal, and generates a first delay signal. A second variable delay circuit delays the input signal, introduces a second delay into a second edge, and generates a second delay signal. A control circuit controls the first variable delay circuit and the second variable delay circuit such that the first delay and the second delay are identical. A generation circuit combines the first edge of the first delay signal and the second edge of the second delay signal, and generates a third delay signal.
    Type: Grant
    Filed: July 27, 2006
    Date of Patent: April 28, 2009
    Assignee: Fujitsu Microelectronics Limited
    Inventors: Katsuhiko Ariyoshi, Souyou Setsu, Ryusuke Obara
  • Delay control circuit
    Publication number: 20070222494
    Abstract: A first variable delay circuit delays an input signal, introduces a first delay into a first edge of the input signal, and generates a first delay signal. A second variable delay circuit delays the input signal, introduces a second delay into a second edge, and generates a second delay signal. A control circuit controls the first variable delay circuit and the second variable delay circuit such that the first delay and the second delay are identical. A generation circuit combines the first edge of the first delay signal and the second edge of the second delay signal, and generates a third delay signal.
    Type: Application
    Filed: July 27, 2006
    Publication date: September 27, 2007
    Inventors: Katsuhiko Ariyoshi, Souyou Setsu, Ryusuke Obara