Abstract: A semiconductor integrated circuit has a first functional block, a second functional block, and a signal line routed from the first functional block to the second functional block in a metal interconnection layer. A complementary pair of metal-oxide-semiconductor circuits with source, gate, and drain terminals are located near the signal line between the first and second functional blocks. The drain terminals extend to the same metal interconnection layer as the signal line, but are not connected to the signal line. The circuit can be redesigned to invert the signal transmitted on the signal line by altering a single mask defining the metal interconnection layer, so as to divide the signal line into a first part connected to the gate terminals and a second part connected to the drain terminals of the complementary pair of metal-oxide-semiconductor circuits.

Abstract: To provide a variable dividing circuit having a high operational speed. The variable dividing circuit includes a shift register configured by cascade connection of D-type flip-flops (D11, D12, . . . , D1n) with an initializing means by clock synchronization; and a multiplexer 12 for selecting any one of output signals at respective stages of the shift register; wherein the variable dividing circuit initializes each stage of the D-type flip-flops. In this case, in an input terminal 10 of the flip-flop at the first stage, a signal at an H level or at an L level is inputted in accordance with an initializing means.

Abstract: A semiconductor integrated circuit has a first functional block, a second functional block, and a signal line routed from the first functional block to the second functional block in a metal interconnection layer. A complementary pair of metal-oxide-semiconductor circuits with source, gate, and drain terminals are located near the signal line between the first and second functional blocks. The drain terminals extend to the same metal interconnection layer as the signal line, but are not connected to the signal line. The circuit can be redesigned to invert the signal transmitted on the signal line by altering a single mask defining the metal interconnection layer, so as to divide the signal line into a first part connected to the gate terminals and a second part connected to the drain terminals of the complementary pair of metal-oxide-semiconductor circuits.

Abstract: To provide a variable dividing circuit having a high operational speed. The variable dividing circuit includes a shift register configured by cascade connection of D-type flip-flops (D11, D12, . . . , D1n) with an initializing means by clock synchronization; and a multiplexer 12 for selecting any one of output signals at respective stages of the shift register; wherein the variable dividing circuit initializes each stage of the D-type flip-flops. In this case, in an input terminal 10 of the flip-flop at the first stage, a signal at an H level or at an L level is inputted in accordance with an initializing means.

Abstract: A frequency multiplier circuit outputs a desired frequency, wherein a frequency of a reference clock is divided by 4 by a frequency divider, the frequency of a unit clock is divided by 2 by another frequency divider and the output of these dividers are provided to an AND gate. A variable frequency divider divides the frequency of an output from the AND gate by n. An up-counter counts the number of pulses of the output from the variable frequency divider. Another variable frequency divider divides the frequency of the unit clock by the number of pulses to output a signal having a frequency of the reference clock multiplied by n.