Abstract: An electrostatic discharge protection circuit capable of clamping both positive and negative ESD events and passing signals is provided. Generally, the circuit includes a p-channel field-effect transistor (PFET) clamp coupled to a pin to be protected, the PFET clamp including a plurality of PFETs in a DN-well, an n-channel field-effect transistors (NFET) clamp coupled between ground and the pin through the PFET clamp, the NFET clamp including a plurality of NFETs coupled in series, and a bias network for biasing a voltage of the DN well to substantially equal a voltage on the pin when the voltage on the pin is greater than ground potential, and to ground potential when the pin voltage is less than ground potential. The plurality of are PFETs coupled in parallel between the pin and the NFET clamp, each of the PFETs is coupled to the pin though one of a plurality ballast resistors.

Abstract: An electrostatic discharge protection circuit capable of clamping both positive and negative ESD events and passing signals is provided. Generally, the circuit includes a p-channel field-effect transistor (PFET) clamp coupled to a pin to be protected, the PFET clamp including a plurality of PFETs in a DN-well, an n-channel field-effect transistors (NFET) clamp coupled between ground and the pin through the PFET clamp, the NFET clamp including a plurality of NFETs coupled in series, and a bias network for biasing a voltage of the DN well to substantially equal a voltage on the pin when the voltage on the pin is greater than ground potential, and to ground potential when the pin voltage is less than ground potential. The plurality of are PFETs coupled in parallel between the pin and the NFET clamp, each of the PFETs is coupled to the pin though one of a plurality ballast resistors.

Abstract: An electrostatic discharge protection circuit capable of clamping both positive and negative ESD events and passing signals is provided. Generally, the circuit includes a p-channel field-effect transistor (PFET) clamp coupled to a pin to be protected, the PFET clamp including a plurality of PFETs in a DN-well, an n-channel field-effect transistors (NFET) clamp coupled between ground and the pin through the PFET clamp, the NFET clamp including a plurality of NFETs coupled in series, and a bias network for biasing a voltage of the DN well to substantially equal a voltage on the pin when the voltage on the pin is greater than ground potential, and to ground potential when the pin voltage is less than ground potential. The plurality of are PFETs coupled in parallel between the pin and the NFET clamp, each of the PFETs is coupled to the pin though one of a plurality ballast resistors.

Abstract: A control circuit for controlling a power supply including a first switch and a second switch coupled in series between a first potential and a second potential. The control circuit includes a detection circuit that detects a magnitude relation of a voltage value at a node between the first and second switches and a reference value during a period in which the first switch and the second switch are inactivated. The detection circuit generates a control signal corresponding to the magnitude relation. A regulation circuit regulates a switching timing of the second switch in response to the control signal to decrease a difference between the voltage value at the node and the reference value.

Abstract: A control circuit for controlling a power supply including a first switch and a second switch coupled in series between a first potential and a second potential. The control circuit includes a detection circuit that detects a magnitude relation of a voltage value at a node between the first and second switches and a reference value during a period in which the first switch and the second switch are inactivated. The detection circuit generates a control signal corresponding to the magnitude relation. A regulation circuit regulates a switching timing of the second switch in response to the control signal to decrease a difference between the voltage value at the node and the reference value.

Abstract: A DC-DC converter has an error amplifier, a first control unit and an oscillator. The error amplifier amplifies an error voltage between an output voltage and a set voltage, the output voltage being outputted from an inductance element by feeding an input voltage to an inductance element in a predetermined cycle. The first control unit controls the output voltage to a set voltage by causing a switching operation of a switch element in response to an output of the error amplifier, the switch element forming a path for input voltage feed to the inductance. The oscillator generates a periodical signal at the time of switching the switch element. The oscillator handles an oscillation cycle as a short cycle in comparison to any prior cycles, in response to a drop in the output voltage from the set voltage by an amount equivalent to a first voltage value or more.

Abstract: A control circuit for controlling a power supply including a first switch and a second switch coupled in series between a first potential and a second potential. The control circuit includes a detection circuit that detects a magnitude relation of a voltage value at a node between the first and second switches and a reference value during a period in which the first switch and the second switch are inactivated. The detection circuit generates a control signal corresponding to the magnitude relation. A regulation circuit regulates a switching timing of the second switch in response to the control signal to decrease a difference between the voltage value at the node and the reference value.

Abstract: To provide a control circuit and control method of a step-up/step-down type DC-DC converter capable of realizing high efficiency. In a state (1), a terminal Tx of a choke coil L1 is connected to an input terminal Tin, and a terminal Ty is connected to a reference potential. In a state (2), the terminal Tx is connected to the reference potential, and the terminal Ty is connected to an output terminal Tout. In the state (3), the terminal Tx is connected to the input terminal Tin, and the terminal Ty is connected to the output terminal Tout. A first period operation TO1 is constituted by the states (1) and (2), and a second period operation TO2 is constituted by the states (1) and (3). A second period T2, in which the second period operation TO2 is performed, is a value n times as long as a first period T1, in which the first period operation TO1 is performed. In the second period operation TO2, the state (1) is switched to the state (3) so that an increasing slope of an inductor current IL is reduced.

Abstract: A first power supply line and having a first conductivity type a second transistor coupled between the first transistor and a second power supply line, and having the first conductivity type an output unit driving a first control signal causing the first transistor to become conductive, based on a drive voltage, and outputting the first control signal to the first transistor and a boot strap circuit including a capacitor having a first end coupled to a node of the first transistor and the second transistor and supplying the output unit with the drive voltage based on the capacitor, wherein an electric potential of the first end is reduced before the first transistor becomes conductive.

Abstract: According to one aspect of the invention, a DC-DC converter including a soft-start function of a soft start in response to a soft-start signal, comprises: a detection circuit that detects whether the soft-start signal is active at an end of a soft-start operation; and an output voltage control circuit that controls an output voltage based on detection result of the detection circuit.

Abstract: To provide a control circuit for a synchronous rectifier-type DC-DC converter, a synchronous rectifier-type DC-DC converter and a control method thereof in which, in a light load state and a no-load state, an output voltage can be dropped to thus prevent an overshoot state from continuing.

Abstract: A DC-DC converter reducing reverse current and maintaining high conversion efficiency under a light load. The DC-DC converter perform pulse width modulation (PWM) or pulse frequency modulation (PFM) and includes a drive control circuit generating a first drive signal and a second drive signal activating and inactivating a first transistor and a second transistor in a complementary manner. A reversed flow detection circuit detects current flowing to the second transistor and generates a detection signal controlling activation and inactivation of the second transistor. A detection signal invalidation circuit, coupled to the reversed flow detection circuit and the drive control circuit, receiving an operation switch signal and invalidating the detection signal in response to the operation switch signal during at least a certain period of the PWM.

Abstract: To provide a control circuit of a current mode DC-DC converter, a current mode DC-DC converter and a control method thereof having excellent high-speed responsiveness with respect to fluctuations in output voltage. The control circuit of the current mode DC-DC converter serves as a DC-DC converter 1 that controls a peak value of a coil current and comprises a window comparator that detects whether an output voltage VOUT is within a predetermined voltage range including a target voltage, and a peak current setting unit that sets a peak current setting value of a coil current to a lower limit value or an upper limit value in response to a high or low voltage level of the output voltage VOUT, in the case that the output voltage VOUT is not within the predetermined voltage range including the target voltage.

Abstract: A DC-DC converter has an error amplifier, a first control unit and an oscillator. The error amplifier amplifies an error voltage between an output voltage and a set voltage, the output voltage being outputted from an inductance element by feeding an input voltage to an inductance element in a predetermined cycle. The first control unit: controls the output voltage to a set voltage by causing a switching operation of a switch element in response to an output of the error amplifier, the switch element forming a path for input voltage feed to the inductance. The oscillator generates a periodical signal at the time of switching the switch element. The oscillator handles an oscillation cycle as a short cycle in comparison to any prior cycles, in response to a drop in the output voltage from the set voltage by an amount equivalent to a first voltage value or more.

Abstract: A first power supply line and having a first conductivity type a second transistor coupled between the first transistor and a second power supply line, and having the first conductivity type an output unit driving a first control signal causing the first transistor to become conductive, based on a drive voltage, and outputting the first control signal to the first transistor and a boot strap circuit including a capacitor having a first end coupled to a node of the first transistor and the second transistor and supplying the output unit with the drive voltage based on the capacitor, wherein an electric potential of the first end is reduced before the first transistor becomes conductive.

Abstract: According to one aspect of the invention, a DC-DC converter including a soft-start function of a soft start in response to a soft-start signal, comprises: a detection circuit that detects whether the soft-start signal is active at an end of a soft-start operation; and an output voltage control circuit that controls an output voltage based on detection result of the detection circuit.

Abstract: A DC-DC converter reducing reverse current and maintaining high conversion efficiency under a light load. The DC-DC converter perform pulse width modulation (PWM) or pulse frequency modulation (PFM) and includes a drive control circuit generating a first drive signal and a second drive signal activating and inactivating a first transistor and a second transistor in a complementary manner. A reversed flow detection circuit detects current flowing to the second transistor and generates a detection signal controlling activation and inactivation of the second transistor. A detection signal invalidation circuit, coupled to the reversed flow detection circuit and the drive control circuit, receiving an operation switch signal and invalidating the detection signal in response to the operation switch signal during at least a certain period of the PWM.

Abstract: To provide a control circuit for a synchronous rectifier-type DC-DC converter, a synchronous rectifier-type DC-DC converter and a control method thereof in which, in a light load state and a no-load state, an output voltage can be dropped to thus prevent an overshoot state from continuing.

Abstract: To provide a control circuit of a current mode DC-DC converter, a current mode DC-DC converter and a control method thereof having excellent high-speed responsiveness with respect to fluctuations in output voltage. The control circuit of the current mode DC-DC converter serves as a DC-DC converter 1 that controls a peak value of a coil current and comprises a window comparator that detects whether an output voltage VOUT is within a predetermined voltage range including a target voltage, and a peak current setting unit that sets a peak current setting value of a coil current to a lower limit value or an upper limit value in response to a high or low voltage level of the output voltage VOUT, in the case that the output voltage VOUT is not within the predetermined voltage range including the target voltage.

Abstract: To provide a control circuit and control method of a step-up/step-down type DC-DC converter capable of realizing high efficiency. In a state (1), a terminal Tx of a choke coil L1 is connected to an input terminal Tin, and a terminal Ty is connected to a reference potential. In a state (2), the terminal Tx is connected to the reference potential, and the terminal Ty is connected to an output terminal Tout. In the state (3), the terminal Tx is connected to the input terminal Tin, and the terminal Ty is connected to the output terminal Tout. A first period operation TO1 is constituted by the states (1) and (2), and a second period operation TO2 is constituted by the states (1) and (3). A second period T2, in which the second period operation TO2 is performed, is a value n times as long as a first period T1, in which the first period operation TO1 is performed. In the second period operation TO2, the state (1) is switched to the state (3) so that an increasing slope of an inductor current IL is reduced.