Abstract: According to an embodiment, an information processing device switching between a secure mode and a non-secure mode to operate, includes one or more processors configured to perform: implementing a secure OS which operates in the secure mode; implementing a non-secure OS which operates in the non-secure mode; acquiring initialization process information autonomously in the secure mode, the initialization process information relating to an initialization process which the non-secure OS executes for a shared resource shared by the secure OS and the non-secure OS; and enabling, based on the initialization process information, the shared resource to be shared and used by the secure OS and the non-secure OS.

Abstract: According to an embodiment, an information processing device operates while switching between a secure mode and a non-secure mode. The information processing device includes processing circuitry. The processing circuitry is configured to function as a switching unit. The switching unit switches a mode from the secure mode to the non-secure mode at the time when the information processing device is operating in the secure mode.

Abstract: According to an embodiment, an information processing device includes a monitoring circuit, a non-secure processing circuit, a secure processing circuit, memory access control circuit. The monitoring circuit switches mode between a non-secure mode and a secure mode. The non-secure processing circuit runs in the non-secure mode, and reads communication data from and writes communication data in a shared memory. The secure processing circuit runs in the secure mode, and reads the communication data from the shared memory and writes the communication data in a storage. The memory access control circuit manages access from the non-secure processing circuit and the secure processing circuit based on a memory access control table in which physical addresses in the shared memory are associated with state information either indicating a locked state for not allowing writing but allowing reading by the non-secure processing circuit or indicating an unlocked state attained by cancelling the locked state.

Abstract: According to an embodiment, an information processing device switching between a secure mode and a non-secure mode to operate, includes one or more processors configured to perform: implementing a secure OS which operates in the secure mode; implementing a non-secure OS which operates in the non-secure mode; acquiring initialization process information autonomously in the secure mode, the initialization process information relating to an initialization process which the non-secure OS executes for a shared resource shared by the secure OS and the non-secure OS; and enabling, based on the initialization process information, the shared resource to be shared and used by the secure OS and the non-secure OS.

Abstract: According to an embodiment, an information processing device operates while switching between a secure mode and a non-secure mode. The information processing device includes processing circuitry. The processing circuitry is configured to function as a switching unit. The switching unit switches a mode from the secure mode to the non-secure mode at the time when the information processing device is operating in the secure mode.

Abstract: According to an embodiment, a data storage device includes a data accumulation unit, a bus interface, and a processor. The processor is configured to control operation of the data storage device so as to spontaneously acquire data from an in-vehicle network via the bus interface and store the data in the data accumulation unit. The processor includes a message processing unit and a data access processing unit. The message processing unit is configured to transmit and receive messages, via the bus interface, to and from an electronic control unit or an external device connected to the in-vehicle network. The data access processing unit is configured to command the data accumulation unit to write and read data. Data included in a message received by the message processing unit is written in the data accumulation unit in accordance with a command of the data access processing unit.

Abstract: According to an embodiment, an information processing device includes a monitoring circuit, a non-secure processing circuit, a secure processing circuit, memory access control circuit. The monitoring circuit switches mode between a non-secure mode and a secure mode. The non-secure processing circuit runs in the non-secure mode, and reads communication data from and writes communication data in a shared memory. The secure processing circuit runs in the secure mode, and reads the communication data from the shared memory and writes the communication data in a storage. The memory access control circuit manages access from the non-secure processing circuit and the secure processing circuit based on a memory access control table in which physical addresses in the shared memory are associated with state information either indicating a locked state for not allowing writing but allowing reading by the non-secure processing circuit or indicating an unlocked state attained by cancelling the locked state.

Abstract: According to an embodiment, a data storage device includes a data accumulation unit, a bus interface, and a processor. The processor is configured to control operation of the data storage device so as to spontaneously acquire data from an in-vehicle network via the bus interface and store the data in the data accumulation unit. The processor includes a message processing unit and a data access processing unit. The message processing unit is configured to transmit and receive messages, via the bus interface, to and from an electronic control unit or an external device connected to the in-vehicle network. The data access processing unit is configured to command the data accumulation unit to write and read data. Data included in a message received by the message processing unit is written in the data accumulation unit in accordance with a command of the data access processing unit.

Abstract: According to one embodiment, an information processing apparatus includes a processor and a memory. The processor operates in a first state and a second state. The memory includes a first region and a second region. A first program code is written in the second region. The first program code is executed when a call of the function provided by an operation system is invoked. A second program code is written in the first region. The processor executes the second program code to replace a first instruction included in the first program code with a second instruction. The second instruction is for switching the second state and the first state.

Abstract: According to one embodiment, an information processing apparatus includes a processor, a main memory, and a memory controller. The memory controller executes an access restriction for each memory region. A first program decodes a protected program which was encrypted in a secure mode. The first program places the protected program which was decoded in a memory region. A second program executes the protected program in a secure mode. The processor places a code region and a protected data region in the protected program which was decoded in a memory region having an access restriction by using the first program. When an access to the protected data region is confirmed, the processor confirms by using the second program that the access is caused by a command from the code region placed by the first program, and then, executes the command.

Abstract: According to one embodiment, an information processing apparatus includes a processor, a main memory, and a memory controller. The memory controller executes an access restriction for each memory region. A first program decodes a protected program which was encrypted in a secure mode. The first program places the protected program which was decoded in a memory region. A second program executes the protected program in a secure mode. The processor places a code region and a protected data region in the protected program which was decoded in a memory region having an access restriction by using the first program. When an access to the protected data region is confirmed, the processor confirms by using the second program that the access is caused by a command from the code region placed by the first program, and then, executes the command.