Patents by Inventor Ryuta Watanabe

Ryuta Watanabe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240132736
    Abstract: An object is to obtain a white ink which is easy to redisperse and is re-dispersible by being shaken several tens of times with weak force at most, or alternatively, without being shaken. As a solution, a white ink composition is provided which contains 50.0% by mass or less of a titanium oxide pigment treated with silica, alumina, and contains an organic compound in a solid content of the white ink composition, and contains 5.0 parts by mass or more of an alkali-soluble resin whose weight-average molecular weight is 28,000 to 100,000 relative to 100 parts by mass of the titanium oxide pigment, and further contains a water-dispersible resin and water.
    Type: Application
    Filed: November 16, 2021
    Publication date: April 25, 2024
    Inventors: Hiroyuki KONISHI, Yuya WATANABE, Ryuta NODA, Masaki MURAKAMI, Satoshi HIRAKAWA
  • Publication number: 20240120664
    Abstract: An antenna device includes an array antenna configured to radiate a radio wave. The array antenna includes at least four radiating elements arranged substantially parallel to a beam scanning plane of the radio wave. The at least four radiating elements are arranged substantially parallel to a first principal surface of window glass for a building, with the antenna device arranged such that the array antenna is arranged at the first principal surface of the window glass in a non-contact manner and such that the radio wave is radiated toward a second principal surface of the window glass opposite from the first principal surface.
    Type: Application
    Filed: December 13, 2023
    Publication date: April 11, 2024
    Applicant: AGC Inc.
    Inventors: Yasuo MORIMOTO, Fuminori WATANABE, Shimpei NAGAE, Ryuta SONODA, Tetsuya HIRAMATSU
  • Publication number: 20240113690
    Abstract: A method for manufacturing a vibrator includes a preparation step of preparing a quartz crystal substrate having a first surface and a second surface which are in a front and back relationship, a first film formation step of forming a first stacked body by sequentially stacking a first underlying film, a second underlying film, and a first protective film at the first surface, a first patterning step of patterning the first stacked body in a manner in which the first underlying film, the second underlying film, and the first protective film remain in a region of an element formation region other than a first groove formation region and a second groove formation region, the first underlying film and the second underlying film remain in the first groove formation region, and the first underlying film remains in the second groove formation region, and a first dry etching step of dry etching the quartz crystal substrate from the first surface through the first stacked body.
    Type: Application
    Filed: September 27, 2023
    Publication date: April 4, 2024
    Inventors: Tsukasa Watanabe, Keiichi Yamaguchi, Shigeru Shiraishi, Ryuta Nishizawa
  • Publication number: 20240113691
    Abstract: A method for manufacturing a vibrator includes a preparation step of preparing a quartz crystal substrate having a first surface and a second surface which are in a front and back relationship, a first protective film formation step of forming a first protective film in a second groove formation region when a region of the quartz crystal substrate where the vibrator is formed is referred to as an element formation region, a region where the first groove is formed is referred to as a first groove formation region, and a region where the second groove is formed is referred to as the second groove formation region, a second protective film formation step of forming, in the first groove formation region, a second protective film having a lower etching rate than the first protective film, a third protective film formation step of forming a third protective film in a region of the element formation region other than the first groove formation region and the second groove formation region, and a first dry etching st
    Type: Application
    Filed: September 27, 2023
    Publication date: April 4, 2024
    Inventors: Tsukasa Watanabe, Keiichi Yamaguchi, Shigeru Shiraishi, Ryuta Nishizawa
  • Publication number: 20240113692
    Abstract: A method for manufacturing a vibrator includes a preparation step of preparing a quartz crystal substrate having a first surface and a second surface which are in a front and back relationship, a first protective film formation step of forming a first protective film in a region of an element formation region other than a first groove formation region and a second groove formation region when a region of the quartz crystal substrate where the vibrator is formed is referred to as the element formation region, a region where the first groove is formed is referred to as the first groove formation region, and a region where the second groove is formed is referred to as the second groove formation region, a first dry etching step of dry etching the quartz crystal substrate from the first surface through the first protective film, a second protective film formation step of forming a second protective film in the first groove formation region, and a second dry etching step of dry etching the quartz crystal substrate
    Type: Application
    Filed: September 27, 2023
    Publication date: April 4, 2024
    Inventors: Tsukasa Watanabe, Keiichi Yamaguchi, Shigeru Shiraishi, Ryuta Nishizawa
  • Publication number: 20240075410
    Abstract: There is provided a gas solution supply apparatus capable of preventing bubbles from being generated in use at a point-of-use even if gas solution to be provided to a point-of-use has a high concentration. The gas solution supply apparatus 1 includes: a gas dissolving unit 4 that dissolves a source gas in a source liquid to produce a first gas solution; a first gas-liquid separator 10 that stores the first gas solution produced and produces a second gas solution through gas-liquid separation of the first gas solution; a pressure reducer 17 that depressurizes the second gas solution produced in the first gas-liquid separator 10; and a second gas-liquid separator 12 that stores the depressurized second gas solution and produces a third gas solution through gas-liquid separation of the second gas solution. The third gas solution is supplied to a point-of-use.
    Type: Application
    Filed: August 2, 2023
    Publication date: March 7, 2024
    Inventors: Suguru OZAWA, Yuji ARAKI, Yoichi NAKAGAWA, Toshifumi WATANABE, Risa KIMURA, Ryuta KATO
  • Publication number: 20240063164
    Abstract: The power semiconductor apparatus includes: a semiconductor device 401; a bonding layer on chip 416 disposed on an upper surface of the semiconductor device; and a metal lead 419 disposed on the upper surface of the semiconductor device and bonded to the bonding layer on chip, wherein the metal lead 420 has a three-laminated structure including: a second metal layer 420b having a CTE equal to or less than 5×10?6/° C., for example; and a first metal layer 420a and a third metal layer 420c sandwiching the second metal layer and having a CTE equal to or greater than the CTE of the second metal layer. Provided is a power semiconductor apparatus capable of improving reliability thereof by reducing a thermal stress to a bonding layer between a semiconductor power device and a metal lead positioned on an upper surface thereof, and reducing a resistance of the metal lead.
    Type: Application
    Filed: October 27, 2023
    Publication date: February 22, 2024
    Inventors: Takukazu OTSUKA, Seita IWAHASHI, Maiko HATANO, Ryuta WATANABE, Katsuhiko YOSHIHARA
  • Publication number: 20240055355
    Abstract: A semiconductor device includes an insulation layer, a support layer located on the insulation layer and containing a metal, and a semiconductor element bonded to the support layer. The semiconductor element includes an element metal layer facing the support layer. A solid-phase diffusion bonding layer is interposed between the support layer and the element metal layer. The insulation layer is lower in Vickers hardness than the support layer.
    Type: Application
    Filed: October 24, 2023
    Publication date: February 15, 2024
    Inventors: Ryuta WATANABE, Takukazu OTSUKA
  • Publication number: 20240027750
    Abstract: An optical line sensor reads an inspection object conveyed in a sub-scanning direction by a reading line L extending in a main scanning direction and includes a plurality of light-receiving lenses 11 and a plurality of light-receiving elements. The plurality of light-receiving lenses 11 are arranged along the main scanning direction. The plurality of light-receiving elements are arranged linearly along the main scanning direction, and receive light transmitted through the plurality of light-receiving, lenses 11. The plurality of light-receiving lenses 11 are arranged to be separated from each other by a diameter of the light-receiving lens 11 or longer. A plurality of light-receiving elements 121 form at least one row or more of the reading lines L.
    Type: Application
    Filed: October 1, 2021
    Publication date: January 25, 2024
    Applicant: VIENEX CORPORATION
    Inventors: Ryuta WATANABE, Osamu IWASAKI
  • Patent number: 11848295
    Abstract: The power semiconductor apparatus includes: a semiconductor device 401; a bonding layer on chip 416 disposed on an upper surface of the semiconductor device; and a metal lead 419 disposed on the upper surface of the semiconductor device and bonded to the bonding layer on chip, wherein the metal lead 420 has a three-laminated structure including: a second metal layer 420b having a CTE equal to or less than 5×10?6/° C., for example; and a first metal layer 420a and a third metal layer 420c sandwiching the second metal layer and having a CTE equal to or greater than the CTE of the second metal layer. Provided is a power semiconductor apparatus capable of improving reliability thereof by reducing a thermal stress to a bonding layer between a semiconductor power device and a metal lead positioned on an upper surface thereof, and reducing a resistance of the metal lead.
    Type: Grant
    Filed: March 2, 2022
    Date of Patent: December 19, 2023
    Assignee: ROHM CO., LTD.
    Inventors: Takukazu Otsuka, Seita Iwahashi, Maiko Hatano, Ryuta Watanabe, Katsuhiko Yoshihara
  • Publication number: 20230402432
    Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a substrate, a mounting layer, switching elements, a moisture-resistant layer and a sealing resin. The substrate has a front surface facing in a thickness direction. The mounting layer is electrically conductive and disposed on the front surface. Each switching element includes an element front surface facing in the same direction in which the front surface faces along the thickness direction, a back surface facing in the opposite direction of the element front surface, and a side surface connected to the element front surface and the back surface. The switching elements are electrically bonded to the mounting layer with their back surfaces facing the front surface. The moisture-resistant layer covers at least one side surface. The sealing resin covers the switching elements and the moisture-resistant layer.
    Type: Application
    Filed: August 25, 2023
    Publication date: December 14, 2023
    Inventors: Kenji HAYASHI, Akihiro SUZAKI, Masaaki MATSUO, Ryuta WATANABE, Makoto IKENAGA
  • Patent number: 11776936
    Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a substrate, amounting layer, switching elements, a moisture-resistant layer and a sealing resin. The substrate has a front surface facing in a thickness direction. The mounting layer is electrically conductive and disposed on the front surface. Each switching element includes an element front surface facing in the same direction in which the front surface faces along the thickness direction, a back surface facing in the opposite direction of the element front surface, and a side surface connected to the element front surface and the back surface. The switching elements are electrically bonded to the mounting layer with their back surfaces facing the front surface. The moisture-resistant layer covers at least one side surface. The sealing resin covers the switching elements and the moisture-resistant layer.
    Type: Grant
    Filed: December 15, 2021
    Date of Patent: October 3, 2023
    Assignee: ROHM CO., LTD.
    Inventors: Kenji Hayashi, Akihiro Suzaki, Masaaki Matsuo, Ryuta Watanabe, Makoto Ikenaga
  • Publication number: 20220189904
    Abstract: The power semiconductor apparatus includes: a semiconductor device 401; a bonding layer on chip 416 disposed on an upper surface of the semiconductor device; and a metal lead 419 disposed on the upper surface of the semiconductor device and bonded to the bonding layer on chip, wherein the metal lead 420 has a three-laminated structure including: a second metal layer 420b having a CTE equal to or less than 5×10?6/° C., for example; and a first metal layer 420a and a third metal layer 420c sandwiching the second metal layer and having a CTE equal to or greater than the CTE of the second metal layer. Provided is a power semiconductor apparatus capable of improving reliability thereof by reducing a thermal stress to a bonding layer between a semiconductor power device and a metal lead positioned on an upper surface thereof, and reducing a resistance of the metal lead.
    Type: Application
    Filed: March 2, 2022
    Publication date: June 16, 2022
    Inventors: Takukazu OTSUKA, Seita IWAHASHI, Maiko HATANO, Ryuta WATANABE, Katsuhiko YOSHIHARA
  • Patent number: 11302665
    Abstract: The power semiconductor apparatus includes: a semiconductor device 401; a bonding layer on chip 416 disposed on an upper surface of the semiconductor device; and a metal lead 419 disposed on the upper surface of the semiconductor device and bonded to the bonding layer on chip, wherein the metal lead 420 has a three-laminated structure including: a second metal layer 420b having a CTE equal to or less than 5×10?6/° C., for example; and a first metal layer 420a and a third metal layer 420c sandwiching the second metal layer and having a CTE equal to or greater than the CTE of the second metal layer. Provided is a power semiconductor apparatus capable of improving reliability thereof by reducing a thermal stress to a bonding layer between a semiconductor power device and a metal lead positioned on an upper surface thereof, and reducing a resistance of the metal lead.
    Type: Grant
    Filed: November 6, 2019
    Date of Patent: April 12, 2022
    Assignee: ROHM CO., LTD.
    Inventors: Takukazu Otsuka, Seita Iwahashi, Maiko Hatano, Ryuta Watanabe, Katsuhiko Yoshihara
  • Publication number: 20220108977
    Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a substrate, amounting layer, switching elements, a moisture-resistant layer and a sealing resin. The substrate has a front surface facing in a thickness direction. The mounting layer is electrically conductive and disposed on the front surface. Each switching element includes an element front surface facing in the same direction in which the front surface faces along the thickness direction, a back surface facing in the opposite direction of the element front surface, and a side surface connected to the element front surface and the back surface. The switching elements are electrically bonded to the mounting layer with their back surfaces facing the front surface. The moisture-resistant layer covers at least one side surface. The sealing resin covers the switching elements and the moisture-resistant layer.
    Type: Application
    Filed: December 15, 2021
    Publication date: April 7, 2022
    Inventors: Kenji HAYASHI, Akihiro SUZAKI, Masaaki MATSUO, Ryuta WATANABE, Makoto IKENAGA
  • Patent number: 11233037
    Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a substrate, amounting layer, switching elements, a moisture-resistant layer and a sealing resin. The substrate has a front surface facing in a thickness direction. The mounting layer is electrically conductive and disposed on the front surface. Each switching element includes an element front surface facing in the same direction in which the front surface faces along the thickness direction, a back surface facing in the opposite direction of the element front surface, and a side surface connected to the element front surface and the back surface. The switching elements are electrically bonded to the mounting layer with their back surfaces facing the front surface. The moisture-resistant layer covers at least one side surface. The sealing resin covers the switching elements and the moisture-resistant layer.
    Type: Grant
    Filed: April 18, 2018
    Date of Patent: January 25, 2022
    Assignee: ROHM CO., LTD.
    Inventors: Kenji Hayashi, Akihiro Suzaki, Masaaki Matsuo, Ryuta Watanabe, Makoto Ikenaga
  • Publication number: 20210134762
    Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a substrate, amounting layer, switching elements, a moisture-resistant layer and a sealing resin. The substrate has a front surface facing in a thickness direction. The mounting layer is electrically conductive and disposed on the front surface. Each switching element includes an element front surface facing in the same direction in which the front surface faces along the thickness direction, a back surface facing in the opposite direction of the element front surface, and a side surface connected to the element front surface and the back surface. The switching elements are electrically bonded to the mounting layer with their back surfaces facing the front surface. The moisture-resistant layer covers at least one side surface. The sealing resin covers the switching elements and the moisture-resistant layer.
    Type: Application
    Filed: April 18, 2018
    Publication date: May 6, 2021
    Inventors: Kenji HAYASHI, Akihiro SUZAKI, Masaaki MATSUO, Ryuta WATANABE, Makoto IKENAGA
  • Publication number: 20200075529
    Abstract: The power semiconductor apparatus includes: a semiconductor device 401; a bonding layer on chip 416 disposed on an upper surface of the semiconductor device; and a metal lead 419 disposed on the upper surface of the semiconductor device and bonded to the bonding layer on chip, wherein the metal lead 420 has a three-laminated structure including: a second metal layer 420b having a CTE equal to or less than 5×10?6/° C., for example; and a first metal layer 420a and a third metal layer 420c sandwiching the second metal layer and having a CTE equal to or greater than the CTE of the second metal layer. Provided is a power semiconductor apparatus capable of improving reliability thereof by reducing a thermal stress to a bonding layer between a semiconductor power device and a metal lead positioned on an upper surface thereof, and reducing a resistance of the metal lead.
    Type: Application
    Filed: November 6, 2019
    Publication date: March 5, 2020
    Inventors: Takukazu OTSUKA, Seita IWAHASHI, Maiko HATANO, Ryuta WATANABE, Katsuhiko YOSHIHARA
  • Patent number: 6521293
    Abstract: A ceramic-coated blade of a gas turbine and a method of producing the same, in which the thickening of an Al2O3 layer at the interface between a ceramic layer and a primary layer is sufficiently prevented for a long period of time, thereby positively suppressing the separation of the ceramic layer. Using powder of MCrAlY alloy (Co—32%Ni—21%Cr—8%Al—0.5%Y), a primary layer (alloy coating layer) is formed on a surface of a substrate made of a heat-resistant Ni base alloy (Rene'-80). Further, a heat-resistant ceramic layer, comprising a mixture of ion-conductive ZrO2—8wt. %Y2O3 ceramic and insulative ceramic (e.g. Al2O3), is formed on the alloy coating layer. This mixture has a columnar structure in which columnar crystals are grown by a gas phase in a direction of a thickness of the coating, or a porous structure in which flattened particles brought about from molten particles caused to fly at high velocity are laminated.
    Type: Grant
    Filed: February 23, 2000
    Date of Patent: February 18, 2003
    Assignees: Hitachi, Ltd., The Tokyo Electric Power Co.
    Inventors: Yoshitaka Kojima, Hideyuki Arikawa, Mitsuo Haginoya, Katsuo Wada, Ryuta Watanabe, Yoshiaki Matsushita, Shin Yoshino
  • Patent number: 6042951
    Abstract: A ceramic-coated blade of a gas turbine and a method of producing the same, in which the thickening of an Al.sub.2 O.sub.3 layer at the interface between a ceramic layer and a primary layer is sufficiently prevented for a long period of time, thereby positively suppressing the separation of the ceramic layer. Using powder of MCrAlY alloy (Co-32% Ni-21% Cr-8% Al-0.5% Y), a primary layer (alloy coating layer) is formed on a surface of a substrate made of a heat-resistant Ni base alloy (Rene'-80). Further, a heat-resistant ceramic layer, comprising a mixture of ion-conductive ZrO.sub.2 -8 wt. % Y.sub.2 O.sub.3 ceramic and insulative ceramic (e.g. Al.sub.2 O.sub.3), is formed on the alloy coating layer. This mixture has a columnar structure in which columnar crystals are grown by a gas phase in a direction of a thickness of the coating, or a porous structure in which flattened particles brought about from molten particles caused to fly at high velocity are laminated.
    Type: Grant
    Filed: February 2, 1998
    Date of Patent: March 28, 2000
    Assignees: Hitachi, Ltd., The Tokyo Electric Power Co., Inc.
    Inventors: Yoshitaka Kojima, Hideyuki Arikawa, Mitsuo Haginoya, Katsuo Wada, Ryuta Watanabe, Yoshiaki Matsushita, Shin Yoshino