Patents by Inventor Ryuta Watanabe

Ryuta Watanabe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20260091550
    Abstract: A production apparatus for a shaped body containing sedimenting particles and a method for producing a shaped body containing sedimenting particles that can continuously mass-produce shaped bodies containing a fixed amount of sedimenting particles. A production apparatus for a shaped body containing sedimenting particles, the apparatus being provided with an ejection head that ejects a liquid containing sedimenting particles, as a liquid droplet, onto a droplet landing element, and a supply apparatus that supplies the liquid to the ejection head, wherein the supply apparatus includes a storage module that extends in a direction transverse to the vertical direction and that stores the liquid, a supply module that supplies the liquid in the storage module from one end in a central axis direction of the storage module, and an agitation unit that rotates the storage module in a circumferential direction about the central axis of the storage module to agitate the liquid inside the storage module.
    Type: Application
    Filed: September 24, 2025
    Publication date: April 2, 2026
    Applicant: Ricoh Company, Ltd.
    Inventors: Daisuke Arai, Hidekazu Yaginuma, Takahiko Matsumoto, Yusuke Nonoyama, Atsushi Miyaoka, Naoki Satoh, Ryuta Watanabe, Shun Anzai
  • Patent number: 12541096
    Abstract: An optical line sensor reads an inspection object conveyed in a sub-scanning direction by a reading line L extending in a main scanning direction and includes a plurality of light-receiving lenses 11 and a plurality of light-receiving elements. The plurality of light-receiving lenses 11 are arranged along the main scanning direction. The plurality of light-receiving elements are arranged linearly along the main scanning direction, and receive light transmitted through the plurality of light-receiving lenses 11. The plurality of light-receiving lenses 11 are arranged to be separated from each other by a diameter of the light-receiving lens 11 or longer. A plurality of light-receiving elements 121 form at least one row or more of the reading lines L.
    Type: Grant
    Filed: October 1, 2021
    Date of Patent: February 3, 2026
    Assignee: VIENEX CORPORATION
    Inventors: Ryuta Watanabe, Osamu Iwasaki
  • Publication number: 20250354938
    Abstract: A plurality of light receiving lenses are arranged along a main scanning direction. A plurality of light receiving elements are arranged in a line along the main scanning direction, and receive light transmitted through the plurality of light receiving lenses. The plurality of light receiving elements form at least two rows of reading lines. The light receiving lenses constitute a telecentric optical system, and a width W1 in a sub-scanning direction is smaller than a width W2 in the main scanning direction.
    Type: Application
    Filed: March 27, 2023
    Publication date: November 20, 2025
    Inventors: Ryuta WATANABE, Osamu IWASAKI
  • Publication number: 20250357433
    Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a substrate, a mounting layer, switching elements, a moisture-resistant layer and a sealing resin. The substrate has a front surface facing in a thickness direction. The mounting layer is electrically conductive and disposed on the front surface. Each switching element includes an element front surface facing in the same direction in which the front surface faces along the thickness direction, a back surface facing in the opposite direction of the element front surface, and a side surface connected to the element front surface and the back surface. The switching elements are electrically bonded to the mounting layer with their back surfaces facing the front surface. The moisture-resistant layer covers at least one side surface. The sealing resin covers the switching elements and the moisture-resistant layer.
    Type: Application
    Filed: July 28, 2025
    Publication date: November 20, 2025
    Inventors: Kenji HAYASHI, Akihiro SUZAKI, Masaaki MATSUO, Ryuta WATANABE, Makoto IKENAGA
  • Publication number: 20250289019
    Abstract: A liquid droplet forming apparatus includes an ejection head configured to eject liquid droplets of liquid, in which the ejection head includes a tubular liquid holder that holds the liquid, and a vibration unit that covers one end side of the liquid holder, forms a liquid chamber holding the liquid together with the liquid holder, and ejects the liquid droplets on the basis of an electric signal to be applied, the vibration unit includes a vibration element that vibrates on the basis of the electric signal, a membrane that includes an outlet ejecting the liquid droplets, and a resonator that vibrates on the basis of the vibration of the vibration element and transmits the vibration of the vibration element to the membrane by vibrating itself, and the resonator is a plate that overlaps with the membrane as viewed in a plan view and is in contact with the membrane.
    Type: Application
    Filed: January 13, 2025
    Publication date: September 18, 2025
    Applicant: Ricoh Company, Ltd.
    Inventors: Takahiko Matsumoto, Yusuke Nonoyama, Daisuke Arai, Atsushi Miyaoka, Ryuta Watanabe, Hidekazu Yaginuma, Chihiro Kubo, Naoki Satoh
  • Patent number: 12401000
    Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a substrate, a mounting layer, switching elements, a moisture-resistant layer and a sealing resin. The substrate has a front surface facing in a thickness direction. The mounting layer is electrically conductive and disposed on the front surface. Each switching element includes an element front surface facing in the same direction in which the front surface faces along the thickness direction, a back surface facing in the opposite direction of the element front surface, and a side surface connected to the element front surface and the back surface. The switching elements are electrically bonded to the mounting layer with their back surfaces facing the front surface. The moisture-resistant layer covers at least one side surface. The sealing resin covers the switching elements and the moisture-resistant layer.
    Type: Grant
    Filed: August 25, 2023
    Date of Patent: August 26, 2025
    Assignee: ROHM CO., LTD.
    Inventors: Kenji Hayashi, Akihiro Suzaki, Masaaki Matsuo, Ryuta Watanabe, Makoto Ikenaga
  • Patent number: 12191275
    Abstract: The power semiconductor apparatus includes: a semiconductor device 401; a bonding layer on chip 416 disposed on an upper surface of the semiconductor device; and a metal lead 419 disposed on the upper surface of the semiconductor device and bonded to the bonding layer on chip, wherein the metal lead 420 has a three-laminated structure including: a second metal layer 420b having a CTE equal to or less than 5×10?6/° C., for example; and a first metal layer 420a and a third metal layer 420c sandwiching the second metal layer and having a CTE equal to or greater than the CTE of the second metal layer. Provided is a power semiconductor apparatus capable of improving reliability thereof by reducing a thermal stress to a bonding layer between a semiconductor power device and a metal lead positioned on an upper surface thereof, and reducing a resistance of the metal lead.
    Type: Grant
    Filed: October 27, 2023
    Date of Patent: January 7, 2025
    Assignee: ROHM CO., LTD.
    Inventors: Takukazu Otsuka, Seita Iwahashi, Maiko Hatano, Ryuta Watanabe, Katsuhiko Yoshihara
  • Publication number: 20240063164
    Abstract: The power semiconductor apparatus includes: a semiconductor device 401; a bonding layer on chip 416 disposed on an upper surface of the semiconductor device; and a metal lead 419 disposed on the upper surface of the semiconductor device and bonded to the bonding layer on chip, wherein the metal lead 420 has a three-laminated structure including: a second metal layer 420b having a CTE equal to or less than 5×10?6/° C., for example; and a first metal layer 420a and a third metal layer 420c sandwiching the second metal layer and having a CTE equal to or greater than the CTE of the second metal layer. Provided is a power semiconductor apparatus capable of improving reliability thereof by reducing a thermal stress to a bonding layer between a semiconductor power device and a metal lead positioned on an upper surface thereof, and reducing a resistance of the metal lead.
    Type: Application
    Filed: October 27, 2023
    Publication date: February 22, 2024
    Inventors: Takukazu OTSUKA, Seita IWAHASHI, Maiko HATANO, Ryuta WATANABE, Katsuhiko YOSHIHARA
  • Publication number: 20240055355
    Abstract: A semiconductor device includes an insulation layer, a support layer located on the insulation layer and containing a metal, and a semiconductor element bonded to the support layer. The semiconductor element includes an element metal layer facing the support layer. A solid-phase diffusion bonding layer is interposed between the support layer and the element metal layer. The insulation layer is lower in Vickers hardness than the support layer.
    Type: Application
    Filed: October 24, 2023
    Publication date: February 15, 2024
    Inventors: Ryuta WATANABE, Takukazu OTSUKA
  • Publication number: 20240027750
    Abstract: An optical line sensor reads an inspection object conveyed in a sub-scanning direction by a reading line L extending in a main scanning direction and includes a plurality of light-receiving lenses 11 and a plurality of light-receiving elements. The plurality of light-receiving lenses 11 are arranged along the main scanning direction. The plurality of light-receiving elements are arranged linearly along the main scanning direction, and receive light transmitted through the plurality of light-receiving, lenses 11. The plurality of light-receiving lenses 11 are arranged to be separated from each other by a diameter of the light-receiving lens 11 or longer. A plurality of light-receiving elements 121 form at least one row or more of the reading lines L.
    Type: Application
    Filed: October 1, 2021
    Publication date: January 25, 2024
    Applicant: VIENEX CORPORATION
    Inventors: Ryuta WATANABE, Osamu IWASAKI
  • Patent number: 11848295
    Abstract: The power semiconductor apparatus includes: a semiconductor device 401; a bonding layer on chip 416 disposed on an upper surface of the semiconductor device; and a metal lead 419 disposed on the upper surface of the semiconductor device and bonded to the bonding layer on chip, wherein the metal lead 420 has a three-laminated structure including: a second metal layer 420b having a CTE equal to or less than 5×10?6/° C., for example; and a first metal layer 420a and a third metal layer 420c sandwiching the second metal layer and having a CTE equal to or greater than the CTE of the second metal layer. Provided is a power semiconductor apparatus capable of improving reliability thereof by reducing a thermal stress to a bonding layer between a semiconductor power device and a metal lead positioned on an upper surface thereof, and reducing a resistance of the metal lead.
    Type: Grant
    Filed: March 2, 2022
    Date of Patent: December 19, 2023
    Assignee: ROHM CO., LTD.
    Inventors: Takukazu Otsuka, Seita Iwahashi, Maiko Hatano, Ryuta Watanabe, Katsuhiko Yoshihara
  • Publication number: 20230402432
    Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a substrate, a mounting layer, switching elements, a moisture-resistant layer and a sealing resin. The substrate has a front surface facing in a thickness direction. The mounting layer is electrically conductive and disposed on the front surface. Each switching element includes an element front surface facing in the same direction in which the front surface faces along the thickness direction, a back surface facing in the opposite direction of the element front surface, and a side surface connected to the element front surface and the back surface. The switching elements are electrically bonded to the mounting layer with their back surfaces facing the front surface. The moisture-resistant layer covers at least one side surface. The sealing resin covers the switching elements and the moisture-resistant layer.
    Type: Application
    Filed: August 25, 2023
    Publication date: December 14, 2023
    Inventors: Kenji HAYASHI, Akihiro SUZAKI, Masaaki MATSUO, Ryuta WATANABE, Makoto IKENAGA
  • Patent number: 11776936
    Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a substrate, amounting layer, switching elements, a moisture-resistant layer and a sealing resin. The substrate has a front surface facing in a thickness direction. The mounting layer is electrically conductive and disposed on the front surface. Each switching element includes an element front surface facing in the same direction in which the front surface faces along the thickness direction, a back surface facing in the opposite direction of the element front surface, and a side surface connected to the element front surface and the back surface. The switching elements are electrically bonded to the mounting layer with their back surfaces facing the front surface. The moisture-resistant layer covers at least one side surface. The sealing resin covers the switching elements and the moisture-resistant layer.
    Type: Grant
    Filed: December 15, 2021
    Date of Patent: October 3, 2023
    Assignee: ROHM CO., LTD.
    Inventors: Kenji Hayashi, Akihiro Suzaki, Masaaki Matsuo, Ryuta Watanabe, Makoto Ikenaga
  • Publication number: 20220189904
    Abstract: The power semiconductor apparatus includes: a semiconductor device 401; a bonding layer on chip 416 disposed on an upper surface of the semiconductor device; and a metal lead 419 disposed on the upper surface of the semiconductor device and bonded to the bonding layer on chip, wherein the metal lead 420 has a three-laminated structure including: a second metal layer 420b having a CTE equal to or less than 5×10?6/° C., for example; and a first metal layer 420a and a third metal layer 420c sandwiching the second metal layer and having a CTE equal to or greater than the CTE of the second metal layer. Provided is a power semiconductor apparatus capable of improving reliability thereof by reducing a thermal stress to a bonding layer between a semiconductor power device and a metal lead positioned on an upper surface thereof, and reducing a resistance of the metal lead.
    Type: Application
    Filed: March 2, 2022
    Publication date: June 16, 2022
    Inventors: Takukazu OTSUKA, Seita IWAHASHI, Maiko HATANO, Ryuta WATANABE, Katsuhiko YOSHIHARA
  • Patent number: 11302665
    Abstract: The power semiconductor apparatus includes: a semiconductor device 401; a bonding layer on chip 416 disposed on an upper surface of the semiconductor device; and a metal lead 419 disposed on the upper surface of the semiconductor device and bonded to the bonding layer on chip, wherein the metal lead 420 has a three-laminated structure including: a second metal layer 420b having a CTE equal to or less than 5×10?6/° C., for example; and a first metal layer 420a and a third metal layer 420c sandwiching the second metal layer and having a CTE equal to or greater than the CTE of the second metal layer. Provided is a power semiconductor apparatus capable of improving reliability thereof by reducing a thermal stress to a bonding layer between a semiconductor power device and a metal lead positioned on an upper surface thereof, and reducing a resistance of the metal lead.
    Type: Grant
    Filed: November 6, 2019
    Date of Patent: April 12, 2022
    Assignee: ROHM CO., LTD.
    Inventors: Takukazu Otsuka, Seita Iwahashi, Maiko Hatano, Ryuta Watanabe, Katsuhiko Yoshihara
  • Publication number: 20220108977
    Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a substrate, amounting layer, switching elements, a moisture-resistant layer and a sealing resin. The substrate has a front surface facing in a thickness direction. The mounting layer is electrically conductive and disposed on the front surface. Each switching element includes an element front surface facing in the same direction in which the front surface faces along the thickness direction, a back surface facing in the opposite direction of the element front surface, and a side surface connected to the element front surface and the back surface. The switching elements are electrically bonded to the mounting layer with their back surfaces facing the front surface. The moisture-resistant layer covers at least one side surface. The sealing resin covers the switching elements and the moisture-resistant layer.
    Type: Application
    Filed: December 15, 2021
    Publication date: April 7, 2022
    Inventors: Kenji HAYASHI, Akihiro SUZAKI, Masaaki MATSUO, Ryuta WATANABE, Makoto IKENAGA
  • Patent number: 11233037
    Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a substrate, amounting layer, switching elements, a moisture-resistant layer and a sealing resin. The substrate has a front surface facing in a thickness direction. The mounting layer is electrically conductive and disposed on the front surface. Each switching element includes an element front surface facing in the same direction in which the front surface faces along the thickness direction, a back surface facing in the opposite direction of the element front surface, and a side surface connected to the element front surface and the back surface. The switching elements are electrically bonded to the mounting layer with their back surfaces facing the front surface. The moisture-resistant layer covers at least one side surface. The sealing resin covers the switching elements and the moisture-resistant layer.
    Type: Grant
    Filed: April 18, 2018
    Date of Patent: January 25, 2022
    Assignee: ROHM CO., LTD.
    Inventors: Kenji Hayashi, Akihiro Suzaki, Masaaki Matsuo, Ryuta Watanabe, Makoto Ikenaga
  • Publication number: 20210134762
    Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a substrate, amounting layer, switching elements, a moisture-resistant layer and a sealing resin. The substrate has a front surface facing in a thickness direction. The mounting layer is electrically conductive and disposed on the front surface. Each switching element includes an element front surface facing in the same direction in which the front surface faces along the thickness direction, a back surface facing in the opposite direction of the element front surface, and a side surface connected to the element front surface and the back surface. The switching elements are electrically bonded to the mounting layer with their back surfaces facing the front surface. The moisture-resistant layer covers at least one side surface. The sealing resin covers the switching elements and the moisture-resistant layer.
    Type: Application
    Filed: April 18, 2018
    Publication date: May 6, 2021
    Inventors: Kenji HAYASHI, Akihiro SUZAKI, Masaaki MATSUO, Ryuta WATANABE, Makoto IKENAGA
  • Publication number: 20200075529
    Abstract: The power semiconductor apparatus includes: a semiconductor device 401; a bonding layer on chip 416 disposed on an upper surface of the semiconductor device; and a metal lead 419 disposed on the upper surface of the semiconductor device and bonded to the bonding layer on chip, wherein the metal lead 420 has a three-laminated structure including: a second metal layer 420b having a CTE equal to or less than 5×10?6/° C., for example; and a first metal layer 420a and a third metal layer 420c sandwiching the second metal layer and having a CTE equal to or greater than the CTE of the second metal layer. Provided is a power semiconductor apparatus capable of improving reliability thereof by reducing a thermal stress to a bonding layer between a semiconductor power device and a metal lead positioned on an upper surface thereof, and reducing a resistance of the metal lead.
    Type: Application
    Filed: November 6, 2019
    Publication date: March 5, 2020
    Inventors: Takukazu OTSUKA, Seita IWAHASHI, Maiko HATANO, Ryuta WATANABE, Katsuhiko YOSHIHARA
  • Patent number: 6521293
    Abstract: A ceramic-coated blade of a gas turbine and a method of producing the same, in which the thickening of an Al2O3 layer at the interface between a ceramic layer and a primary layer is sufficiently prevented for a long period of time, thereby positively suppressing the separation of the ceramic layer. Using powder of MCrAlY alloy (Co—32%Ni—21%Cr—8%Al—0.5%Y), a primary layer (alloy coating layer) is formed on a surface of a substrate made of a heat-resistant Ni base alloy (Rene'-80). Further, a heat-resistant ceramic layer, comprising a mixture of ion-conductive ZrO2—8wt. %Y2O3 ceramic and insulative ceramic (e.g. Al2O3), is formed on the alloy coating layer. This mixture has a columnar structure in which columnar crystals are grown by a gas phase in a direction of a thickness of the coating, or a porous structure in which flattened particles brought about from molten particles caused to fly at high velocity are laminated.
    Type: Grant
    Filed: February 23, 2000
    Date of Patent: February 18, 2003
    Assignees: Hitachi, Ltd., The Tokyo Electric Power Co.
    Inventors: Yoshitaka Kojima, Hideyuki Arikawa, Mitsuo Haginoya, Katsuo Wada, Ryuta Watanabe, Yoshiaki Matsushita, Shin Yoshino