Abstract: A display system having a frame buffer comprising a plurality of memory planes, a display device for visually displaying images written into the frame buffer, and a controller for controlling image data operations. The display system is provided with an extended raster operation circuitry comprising an intraplane operation unit and an interplane operation unit. Operation results of the circuitry are written back to the frame buffer. The respective operation units perform operations specified by the controller. The intraplane operation unit performs operations on image data in each of the memory planes, separately, while the interplane operation unit performs operations on image data in at least two memory planes selected by the controller. There are no restrictions as to the positional relation between the intraplane operation unit and the interplane operation unit.