Patents by Inventor Ryuu Saitou

Ryuu Saitou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8033721
    Abstract: A temperature sensor circuit is provided that facilitates preventing a too-high overshooting voltage from occurring at an output terminal when a power supply is connected to the temperature sensor circuit. The temperature sensor circuit includes a short-circuiting device, disposed in parallel to depletion mode NMOS, that short-circuits the drain and source of depletion mode NMOS when a power supply is connected; and delay device that transmits a signal for short-circuiting the drain and source of depletion mode NMOS for a certain period from the time point of power supply connection to short-circuiting device for preventing the voltage at output terminal of temperature sensor circuit from overshooting.
    Type: Grant
    Filed: December 15, 2008
    Date of Patent: October 11, 2011
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Takatoshi Ooe, Ryuu Saitou, Morio Iwamizu
  • Patent number: 8006678
    Abstract: A coil failure detection circuit detects a rise of a collector current of an IGBT and a timer circuit measures the length of a rise period. If the rise is not a normal one, an electronic control unit judges that a coil failure has occurred. The electronic control unit turns off the IGBT to prevent misfires and stops a flow of fuel gas to a combustion chamber to prevent melting or deterioration of a catalyst.
    Type: Grant
    Filed: December 4, 2008
    Date of Patent: August 30, 2011
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Tatsuya Naito, Kenichi Ishii, Shigemi Miyazawa, Ryuu Saitou
  • Patent number: 7602022
    Abstract: To prevent the destruction of a semiconductor element due to negative resistance, and to reduce the dynamic resistance of a static electricity prevention diode, the ratio of the maximum electric field intensity during an avalanche and the average electric field in a strong electric field region, as well as the impurity density gradient in the vicinity of the strong electric field region are optimized. During avalanche breakdown, a depletion layer is formed across the entire high resistivity region, and its average electric field is kept to ½ or more of the maximum electric field intensity. The density gradients (the depths and impurity densities) of a p+ region and of an n+ region that form a p-n junction of the diode are controlled so that the density gradient in the neighborhood of the high resistivity region does not have negative resistance with respect to increase of the avalanche current.
    Type: Grant
    Filed: March 14, 2006
    Date of Patent: October 13, 2009
    Assignee: Fuji Electric Device Technology Co., Ltd.
    Inventors: Naoki Kumagai, Hiroshi Kanemaru, Yuiichi Harada, Yoshihiro Ikura, Ryuu Saitou
  • Publication number: 20090153227
    Abstract: A temperature sensor circuit is provided that facilitates preventing a too-high overshooting voltage from occurring at an output terminal when a power supply is connected to the temperature sensor circuit. The temperature sensor circuit includes a short-circuiting device, disposed in parallel to depletion mode NMOS, that short-circuits the drain and source of depletion mode NMOS when a power supply is connected; and delay device that transmits a signal for short-circuiting the drain and source of depletion mode NMOS for a certain period from the time point of power supply connection to short-circuiting device for preventing the voltage at output terminal of temperature sensor circuit from overshooting.
    Type: Application
    Filed: December 15, 2008
    Publication date: June 18, 2009
    Applicant: FUJI ELECTRIC DEVICE TECHNOLOGY CO., LTD.
    Inventors: Takatoshi OOE, Ryuu SAITOU, Morio IWAMIZU
  • Publication number: 20090139505
    Abstract: A coil failure detection circuit detects a rise of a collector current of an IGBT and a timer circuit measures the length of a rise period. If the rise is not a normal one, an electronic control unit judges that a coil failure has occurred. The electronic control unit turns off the IGBT to prevent misfires and stops a flow of fuel gas to a combustion chamber to prevent melting or deterioration of a catalyst.
    Type: Application
    Filed: December 4, 2008
    Publication date: June 4, 2009
    Applicant: FUJI ELECTRIC DEVICE TECHNOLOGY CO., LTD.
    Inventors: Tatsuya NAITO, Kenichi ISHII, Shigemi MIYAZAWA, Ryuu SAITOU
  • Patent number: 7436024
    Abstract: A lateral MOSFET and a method of forming thereof includes a p-type semiconductor substrate, a first n-type well in the surface portion of the semiconductor substrate, an n+-type drain region in the first n-type well, a p-type well in the first n-type well, an n+-type source region in the p-type well, a gate oxide film on the portion of the p-type well between the n+-type source region and the first n-type well, a gate electrode on the gate oxide film, and a second n-type well containing the p-type well therein to increase the n-type impurity concentration in the vicinity of the junction between the p-type well and the first n-type well beneath the gate and to increase the impurity amount and the thickness of the n-type semiconductor region beneath the p-type well. The first and second n-type wells can be overlapping or formed continuous or contiguous with each other. The lateral MOSFET exhibits a high punch-through breakdown voltage suitable for a high-side switch.
    Type: Grant
    Filed: August 3, 2005
    Date of Patent: October 14, 2008
    Assignee: Fuji Electric Device Technology Co., Ltd.
    Inventors: Naoki Kumagai, Yuuichi Harada, Hiroshi Kanemaru, Yoshihiro Ikura, Ryuu Saitou
  • Publication number: 20060231836
    Abstract: To prevent the destruction of a semiconductor element due to negative resistance, and to reduce the dynamic resistance of a static electricity prevention diode, the ratio of the maximum electric field intensity during an avalanche and the average electric field in a strong electric field region, as well as the impurity density gradient in the vicinity of the strong electric field region are optimized. During avalanche breakdown, a depletion layer is formed across the entire high resistivity region, and its average electric field is kept to ½ or more of the maximum electric field intensity. The density gradients (the depths and impurity densities) of a p+ region and of an n+ region that form a p-n junction of the diode are controlled so that the density gradient in the neighborhood of the high resistivity region does not have negative resistance with respect to increase of the avalanche current.
    Type: Application
    Filed: March 14, 2006
    Publication date: October 19, 2006
    Applicant: FUJI ELECTRIC DEVICE TECHNOLOGY CO., LTD.
    Inventors: Naoki Kumagai, Hiroshi Kanemaru, Yuiichi Harada, Yoshihiro Ikura, Ryuu Saitou
  • Publication number: 20060027863
    Abstract: A lateral MOSFET and a method of forming thereof includes a p-type semiconductor substrate, a first n-type well in the surface portion of the semiconductor substrate, an n+-type drain region in the first n-type well, a p-type well in the first n-type well, an n+-type source region in the p-type well, a gate oxide film on the portion of the p-type well between the n+-type source region and the first n-type well, a gate electrode on the gate oxide film, and a second n-type well containing the p-type well therein to increase the n-type impurity concentration in the vicinity of the junction between the p-type well and the first n-type well beneath the gate and to increase the impurity amount and the thickness of the n-type semiconductor region beneath the p-type well. The first and second n-type wells can be overlapping or formed continuous or contiguous with each other. The lateral MOSFET exhibits a high punch-through breakdown voltage suitable for a high-side switch.
    Type: Application
    Filed: August 3, 2005
    Publication date: February 9, 2006
    Applicant: Fuji Electric Device Technology Co., Ltd.
    Inventors: Naoki Kumagai, Yuuichi Harada, Hiroshi Kanemaru, Yoshihiro Ikura, Ryuu Saitou