Patents by Inventor Ryuuta Watanabe
Ryuuta Watanabe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11287709Abstract: An active matrix substrate includes: a signal line provided in an image display region; and a terminal provided in a frame region and electrically connected to the signal line. The terminal includes: a metal layer; a first contact layer located closer to one side in a lamination direction than the metal layer, and electrically connected to the metal layer, a first interlayer insulating layer located closer to the one side in the lamination direction than the first contact layer; and a second contact layer located closer to the one side in the lamination direction than the first interlayer insulating layer, and electrically connected to the first contact layer through a first through-hole formed in the first interlayer insulating layer. The first contact layer is made of a transparent metal oxide or a semiconductor material doped with impurities.Type: GrantFiled: February 6, 2020Date of Patent: March 29, 2022Assignee: PANASONIC LIQUID CRYSTAL DISPLAY CO., LTD.Inventors: Tetsuo Fukami, Kenichirou Nishida, Ryuuta Watanabe, Masahiro Ishii
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Publication number: 20200278587Abstract: An active matrix substrate includes: a signal line provided in an image display region; and a terminal provided in a frame region and electrically connected to the signal line. The terminal includes: a metal layer; a first contact layer located closer to one side in a lamination direction than the metal layer, and electrically connected to the metal layer, a first interlayer insulating layer located closer to the one side in the lamination direction than the first contact layer; and a second contact layer located closer to the one side in the lamination direction than the first interlayer insulating layer, and electrically connected to the first contact layer through a first through-hole formed in the first interlayer insulating layer. The first contact layer is made of a transparent metal oxide or a semiconductor material doped with impurities.Type: ApplicationFiled: February 6, 2020Publication date: September 3, 2020Inventors: Tetsuo FUKAMI, Kenichirou NISHIDA, Ryuuta WATANABE, Masahiro ISHII
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Patent number: 8685631Abstract: A nozzle is moved while supplying a photoresist liquid from a slit. A photoresist layer is formed on a film. A resist pattern which covers a portion of the film is formed from the photoresist layer by photolithography. Inspection of the resist pattern is performed. The photolithography includes an exposure which is performed so as to transfer a latent image to the photoresist layer, and a development of the photoresist layer which is performed so as to leave the latent image. The latent image contains a dummy latent image which extends in an unbroken manner parallel to the longitudinal direction of the slit. The resist pattern contains a dummy resist formed correspondingly to the dummy latent image. The inspection of the resist pattern includes the detection of the presence or non-presence of a cut in the dummy resist in the longitudinal direction.Type: GrantFiled: June 17, 2010Date of Patent: April 1, 2014Assignee: Panasonic Liquid Crystal Display Co., Ltd.Inventors: Yoshihiro Daito, Ryuuta Watanabe, Yoshitaka Imabayashi
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Publication number: 20100323304Abstract: A nozzle is moved while supplying a photoresist liquid from a slit. A photoresist layer is formed on a film. A resist pattern which covers a portion of the film is formed from the photoresist layer by photolithography. Inspection of the resist pattern is performed. The photolithography includes an exposure which is performed so as to transfer a latent image to the photoresist layer, and a development of the photoresist layer which is performed so as to leave the latent image. The latent image contains a dummy latent image which extends in an unbroken manner parallel to the longitudinal direction of the slit. The resist pattern contains a dummy resist formed correspondingly to the dummy latent image. The inspection of the resist pattern includes the detection of the presence or non-presence of a cut in the dummy resist in the longitudinal direction.Type: ApplicationFiled: June 17, 2010Publication date: December 23, 2010Inventors: Yoshihiro DAITO, Ryuuta Watanabe, Yoshitaka Imabayashi
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Patent number: 7576828Abstract: A liquid crystal display device comprises a pair of substrates which are arranged to face each other in an opposed manner while sandwiching liquid crystal therebetween, pixel regions which are formed on a liquid-crystal-side surface of one substrate out of the pair of substrates, and thin film transistors which are formed on respective pixel regions, wherein each thin film transistor includes a gate electrode connected to a gate signal line, a semiconductor layer laminated to the gate electrode by way of an insulation film, a drain electrode formed on the semiconductor layer and connected to a drain signal line, and a source electrode connected to a pixel electrode, and the semiconductor layer is formed in a periodically irregular shape in a zone having a width substantially larger than a width of the source electrode on a side thereof from which at least the source electrode is pulled out.Type: GrantFiled: June 20, 2008Date of Patent: August 18, 2009Assignee: Hitachi, Ltd.Inventors: Takanori Nakayama, Ryuuta Watanabe, Jun Ooida, Yasuko Gotoh, Kaori Miyazaki
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Patent number: 7561243Abstract: A liquid crystal display device comprises a pair of substrates which are arranged to face each other in an opposed manner while sandwiching liquid crystal therebetween, pixel regions which are formed on a liquid-crystal-side surface of one substrate out of the pair of substrates, and thin film transistors which are formed on respective pixel regions, wherein each thin film transistor includes a gate electrode connected to a gate signal line, a semiconductor layer laminated to the gate electrode by way of an insulation film, a drain electrode formed on the semiconductor layer and connected to a drain signal line, and a source electrode connected to a pixel electrode, and the semiconductor layer is formed in a periodically irregular shape in a zone having a width substantially larger than a width of the source electrode on a side thereof from which at least the source electrode is pulled out.Type: GrantFiled: July 9, 2002Date of Patent: July 14, 2009Assignee: Hitachi, Ltd.Inventors: Takanori Nakayama, Ryuuta Watanabe, Jun Ooida, Yasuko Gotoh, Kaori Miyazaki
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Publication number: 20080266476Abstract: A liquid crystal display device comprises a pair of substrates which are arranged to face each other in an opposed manner while sandwiching liquid crystal therebetween, pixel regions which are formed on a liquid-crystal-side surface of one substrate out of the pair of substrates, and thin film transistors which are formed on respective pixel regions, wherein each thin film transistor includes a gate electrode connected to a gate signal line, a semiconductor layer laminated to the gate electrode by way of an insulation film, a drain electrode formed on the semiconductor layer and connected to a drain signal line, and a source electrode connected to a pixel electrode, and the semiconductor layer is formed in a periodically irregular shape in a zone having a width substantially larger than a width of the source electrode on a side thereof from which at least the source electrode is pulled out.Type: ApplicationFiled: June 20, 2008Publication date: October 30, 2008Inventors: Takanori Nakayama, Ryuuta Watanabe, Jun Ooida, Yasuko Gotoh, Kaori Miyazaki
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Publication number: 20030043307Abstract: A liquid crystal display device comprises a pair of substrates which are arranged to face each other in an opposed manner while sandwiching liquid crystal therebetween, pixel regions which are formed on a liquid-crystal-side surface of one substrate out of the pair of substrates, and thin film transistors which are formed on respective pixel regions, wherein each thin film transistor includes a gate electrode connected to a gate signal line, a semiconductor layer laminated to the gate electrode by way of an insulation film, a drain electrode formed on the semiconductor layer and connected to a drain signal line, and a source electrode connected to a pixel electrode, and the semiconductor layer is formed in a periodically irregular shape in a zone having a width substantially larger than a width of the source electrode on a side thereof from which at least the source electrode is pulled out.Type: ApplicationFiled: July 9, 2002Publication date: March 6, 2003Applicant: Hitachi, Ltd.Inventors: Takanori Nakayama, Ryuuta Watanabe, Jun Ooida, Yasuko Gotoh, Kaori Miyazaki