Patents by Inventor Ryuzo Shiraki

Ryuzo Shiraki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8050571
    Abstract: An illumination light receiver includes: a wavelength separation mechanism separating visible light containing optical signal data distributed among wavelengths corresponding to three primary colors into the wavelengths corresponding to the three primary colors; a dispersion restraining mechanism restraining dispersion of light outputted from the wavelength separation mechanism; and a light receiving portion illuminated, separately for each of the separated wavelengths corresponding to the three primary colors, by the light outputted from the dispersion restraining mechanism, the light receiving portion converting the optical signal data into and extracting an electrical signal.
    Type: Grant
    Filed: March 13, 2009
    Date of Patent: November 1, 2011
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Ryuzo Shiraki
  • Publication number: 20090324248
    Abstract: An illumination light receiver includes: a wavelength separation mechanism separating visible light containing optical signal data distributed among wavelengths corresponding to three primary colors into the wavelengths corresponding to the three primary colors; a dispersion restraining mechanism restraining dispersion of light outputted from the wavelength separation mechanism; and a light receiving portion illuminated, separately for each of the separated wavelengths corresponding to the three primary colors, by the light outputted from the dispersion restraining mechanism, the light receiving portion converting the optical signal data into and extracting an electrical signal.
    Type: Application
    Filed: March 13, 2009
    Publication date: December 31, 2009
    Inventor: Ryuzo SHIRAKI
  • Patent number: 4424456
    Abstract: A driver circuit for a charge coupled device which includes a CMOS inverter including a P channel MOS transistor and an N channel MOS transistor for inverting the level of an input control pulse, an output terminal of the CMOS inverter being connected to a charge coupled device such that the P channel MOS transistor functions to charge the equivalent load capacitance of the charge coupled device and the N channel MOS transistor functions to discharge the equivalent load capacitance. A continuously variable DC power supply is provided for applying a variable gate voltage to the gate of at least one of the P and N channel MOS transistors to change the mutual conductance of the transistor so that the time constant of the charge or discharge circuit to the load capacitance can be adjusted to optimize the charge transfer efficiency of the charged coupled device.
    Type: Grant
    Filed: December 23, 1980
    Date of Patent: January 3, 1984
    Assignee: Tokyo Shibaura Denki Kabushiki Kaisha
    Inventors: Ryuzo Shiraki, Seizi Watanabe, Toshio Yuyama
  • Patent number: 4408135
    Abstract: A multi-level signal generating circuit is disclosed which comprises: a first CMOS inverter for inverting an input signal to produce a first output signal having high and low voltage levels; a second CMOS inverter for inverting the input signal to produce a second output signal having high and low voltage levels; at least one of the high and low voltage levels of the second output signals being different from said high and low voltage of said first output signal; and switching circuit operative to drive selectively said first CMOS inverter or said second CMOS inverter in response to a level of a control signal.
    Type: Grant
    Filed: December 16, 1980
    Date of Patent: October 4, 1983
    Assignee: Tokyo Shibaura Denki Kabushiki Kaisha
    Inventors: Toshio Yuyama, Ryuzo Shiraki, Seizi Watanabe
  • Patent number: 4217502
    Abstract: An output circuit is provided in which a first IG-FET of a first conductivity type is connected between a first potential supply terminal and an output terminal and having its substrate controlled by a third potential higher than the first potential of the first potential supply terminal and a second IG-FET of a second conductivity type connected between a second potential supply terminal having a second potential lower than the first potential and the output terminal and having its substrate electrode supplied with the second potential. A control circuit is further provided which receives an input signal and control signal and controls the output circuit to permit the latter to produce one of the first potential, second potential and high impedance state. The output circuit and control circuit are combined to provide a converter circuit for converting the level of a CML (complementary MOS Transistor Logic) to a TTL (Transistor-Transistor Logic).
    Type: Grant
    Filed: September 11, 1978
    Date of Patent: August 12, 1980
    Assignee: Tokyo Shibaura Denki Kabushiki Kaisha
    Inventors: Yasoji Suzuki, Ryuzo Shiraki