Patents by Inventor Sébastien Barasinski
Sébastien Barasinski has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8335121Abstract: A device, and a corresponding method of implementation, for SRAM memory information storage are provided. The device is powered by a supply voltage and includes an array of base cells organized in base columns, and at least one mirror column of at least one mirror cell liable to simulate the behavior of the cells in a base column. The device further includes Emulation means, in a mirror column, of the most restricting cell in a base column, Means for varying a mirror power supply voltage for the mirror column, and Means for copying the mirror power supply voltage in the emulated base column.Type: GrantFiled: July 2, 2010Date of Patent: December 18, 2012Assignee: STMicroelectronics S.A.Inventors: Cyrille Dray, Francois Jacquet, Sébastien Barasinski
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Patent number: 8044728Abstract: An integrated circuit may include an inverter which may include a first transistor of a first conductivity type and a second transistor of a second conductivity type connected in parallel with the first transistor. An input of the inverter may be capable of receiving an oscillating input signal, and which may include an output of the inverter, which is connected to a capacitive device capable of being charged and discharged depending on the state of the first and second transistors being on or off. The inverter may be capable of delivering an oscillating output signal at its output. The integrated circuit may include a selector for transmitting the oscillating output signal and for masking the charging and/or discharging of the capacitive device.Type: GrantFiled: August 18, 2009Date of Patent: October 25, 2011Assignee: STMicroelectronics SAInventor: Sébastien Barasinski
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Publication number: 20100265758Abstract: A device, and a corresponding method of implementation, for SRAM memory information storage are provided. The device is powered by a supply voltage and includes an array of base cells organized in base columns, and at least one mirror column of at least one mirror cell liable to simulate the behavior of the cells in a base column. The device further includes Emulation means, in a mirror column, of the most restricting cell in a base column, Means for varying a mirror power supply voltage for the mirror column, and Means for copying the mirror power supply voltage in the emulated base column.Type: ApplicationFiled: July 2, 2010Publication date: October 21, 2010Applicant: STMicroelectronics SAInventors: Cyrille Dray, Francois Jacquet, Sébastien Barasinski
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Patent number: 7795917Abstract: A buffer circuit includes at least one part that is powered by a supply voltage by means of a first initialization transistor, and connected to the ground by means of a second initialization transistor. The circuit is capable of transferring, between an input and an output, an input signal including at least one rising edge and/or one falling edge. The circuit includes a first CMOS inverter, of which the input is connected to the input of the circuit, and of which the output is mounted in series with the input of a second CMOS inverter, with the output of the second CMOS inverter being connected to the output of the circuit. A circuit creates an overvoltage on one of the two inverters during operation.Type: GrantFiled: January 15, 2008Date of Patent: September 14, 2010Assignee: STMicroelectronics SAInventors: Sebastien Barasinski, Cyrille Dray
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Patent number: 7755927Abstract: A memory device of SRAM type has a memory plan constituted by base memory cells organized in lines and in columns. Each cell of a column is connected between two bit lines which are precharged during a reading operation. Circuitry is provided for generating a precharge voltage of the bit lines which is less than a nominal supply voltage of the device.Type: GrantFiled: December 5, 2007Date of Patent: July 13, 2010Assignee: STMicroelectronics S.A.Inventors: Sébastien Barasinski, François Jacquet, Marc Sabut
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Patent number: 7751229Abstract: A device, and a corresponding method of implementation, for SRAM memory information storage are provided. The device is powered by a supply voltage and includes an array of base cells organized in base columns, and at least one mirror column of at least one mirror cell liable to simulate the behavior of the cells in a base column. The device further includes Emulation means, in a mirror column, of the most restricting cell in a base column, Means for varying a mirror power supply voltage (VDDMMOCK) for the mirror column, and Means for copying the mirror power supply voltage in the emulated base column.Type: GrantFiled: December 28, 2006Date of Patent: July 6, 2010Assignee: STMicroelectronics S.A.Inventors: Cyrille Dray, Francois Jacquet, Sébastien Barasinski
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Publication number: 20100045390Abstract: An integrated circuit may include an inverter which may include a first transistor of a first conductivity type and a second transistor of a second conductivity type connected in parallel with the first transistor. An input of the inverter may be capable of receiving an oscillating input signal, and which may include an output of the inverter, which is connected to a capacitive device capable of being charged and discharged depending on the state of the first and second transistors being on or off. The inverter may be capable of delivering an oscillating output signal at its output. The integrated circuit may include a selector for transmitting the oscillating output signal and for masking the charging and/or discharging of the capacitive device.Type: ApplicationFiled: August 18, 2009Publication date: February 25, 2010Applicant: STMicroelectronics SAInventor: Sebastien BARASINSKI
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Patent number: 7545686Abstract: The invention relates to a device for setting up a write current on at least one write conducting line in an MRAM type integrated circuit memory, including a current mirror composed of a first stage acting as the reference regulated cascode stage receiving all or part of the write current on its input and a second stage acting as the copy regulated cascode stage copying the write current onto the write line.Type: GrantFiled: March 17, 2005Date of Patent: June 9, 2009Assignee: STMicroelectronics S.A.Inventors: Jean Lasseuguette, Cyrille Dray, Sébastien Barasinski
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Publication number: 20080218211Abstract: A buffer circuit includes at least one part that is powered by a supply voltage by means of a first initialization transistor, and connected to the ground by means of a second initialization transistor. The circuit is capable of transferring, between an input and an output, an input signal including at least one rising edge and/or one falling edge. The circuit includes a first CMOS inverter, of which the input is connected to the input of the circuit, and of which the output is mounted in series with the input of a second CMOS inverter, with the output of the second CMOS inverter being connected to the output of the circuit. A circuit creates an overvoltage on one of the two inverters during operation.Type: ApplicationFiled: January 15, 2008Publication date: September 11, 2008Applicant: STMicroelectronics SAInventors: Sebastien Barasinski, Cyrille Dray
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Publication number: 20080144413Abstract: A memory device of SRAM type has a memory plan constituted by base memory cells organized in lines and in columns. Each cell of a column is connected between two bit lines which are precharged during a reading operation. Circuitry is provided for generating a precharge voltage of the bit lines which is less than a nominal supply voltage of the device.Type: ApplicationFiled: December 5, 2007Publication date: June 19, 2008Applicant: STMicroelectronics S.A.Inventors: Sebastien Barasinski, Francois Jacquet, Marc Sabut
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Patent number: 7372728Abstract: A random access memory array includes random access memory elements arranged in a rows and columns. The elements of each row have a word line and a write digit line and the elements of each column have a bit line and a write bit line. A first selection circuit/transistor for each row has a first source-drain path coupled in the write digit line and a gate terminal coupled to the word line. A second selection circuit/transistor for each column has a second source-drain path coupling in the write bit line and a gate terminal coupled to the bit line. A first write signal is applied to one word line to actuate the first selection circuit/transistor for the row corresponding to that one word line and cause a write current to flow through the first source-drain path of the actuated first selection circuit/transistor and the corresponding write digit line to write data into certain memory elements in that row.Type: GrantFiled: April 23, 2007Date of Patent: May 13, 2008Assignees: STMicroelectronics, Inc., STMicroelectronics S.A.Inventors: Cyrille Dray, Christophe Frey, Jean Lasseuguette, Sébastien Barasinski, Richard Fournel
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Publication number: 20070189066Abstract: A random access memory array includes random access memory elements arranged in a rows and columns. The elements of each row have a word line and a write digit line and the elements of each column have a bit line and a write bit line. A first selection circuit/transistor for each row has a first source-drain path coupled in the write digit line and a gate terminal coupled to the word line. A second selection circuit/transistor for each column has a second source-drain path coupling in the write bit line and a gate terminal coupled to the bit line. A first write signal is applied to one word line to actuate the first selection circuit/transistor for the row corresponding to that one word line and cause a write current to flow through the first source-drain path of the actuated first selection circuit/transistor and the corresponding write digit line to write data into certain memory elements in that row.Type: ApplicationFiled: April 23, 2007Publication date: August 16, 2007Inventors: Cyrille Dray, Christophe Frey, Jean Lasseuguette, Sebastien Barasinski, Richard Fournel
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Patent number: 7209383Abstract: A random access memory array includes random access memory elements arranged in a rows and columns. The elements of each row have a word line and a write digit line and the elements of each column have a bit line and a write bit line. A first selection circuit/transistor for each row has a first source-drain path coupled in the write digit line and a gate terminal coupled to the word line. A second selection circuit/transistor for each column has a second source-drain path coupling in the write bit line and a gate terminal coupled to the bit line. A first write signal is applied to one word line to actuate the first selection circuit/transistor for the row corresponding to that one word line and cause a write current to flow through the first source-drain path of the actuated first selection circuit/transistor and the corresponding write digit line to write data into certain memory elements in that row.Type: GrantFiled: June 23, 2005Date of Patent: April 24, 2007Assignee: STMicroelectronics, Inc.Inventors: Cyrille Dray, Christophe Frey, Jean Lasseuguette, Sébastien Barasinski, Richard Fournel
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Patent number: 7139212Abstract: A memory device includes at least one segmented writing line formed by at least one writing segment. A programming circuit is controlled by a line address circuit in a writing mode of the memory device to program at least one memory cell coupled to the segmented writing line. A reading bit line is connected to a reading circuit for reading the contents of the cell in a reading mode of the memory device. The reading bit line cooperates in writing mode with the line address circuit to control the programming circuit of the segmented writing line.Type: GrantFiled: June 14, 2005Date of Patent: November 21, 2006Assignee: STMicroelectronics S.A.Inventors: Cyrille Dray, Sébastien Barasinski, Jean Lasseuguette, Christophe Frey, Richard Fournel
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Publication number: 20060050585Abstract: The invention relates to a device for setting up a write current on at least one write conducting line in an MRAM type integrated circuit memory, including a current mirror composed of a first stage acting as the reference regulated cascode stage receiving all or part of the write current on its input and a second stage acting as the copy regulated cascode stage copying the write current onto the write line.Type: ApplicationFiled: March 17, 2005Publication date: March 9, 2006Applicant: STMicroelectronics S.A.Inventors: Jean Lasseuguette, Cyrille Dray, Sebastien Barasinski
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Publication number: 20050281080Abstract: A random access memory array includes random access memory elements arranged in a rows and columns. The elements of each row have a word line and a write digit line and the elements of each column have a bit line and a write bit line. A first selection circuit/transistor for each row has a first source-drain path coupled in the write digit line and a gate terminal coupled to the word line. A second selection circuit/transistor for each column has a second source-drain path coupling in the write bit line and a gate terminal coupled to the bit line. A first write signal is applied to one word line to actuate the first selection circuit/transistor for the row corresponding to that one word line and cause a write current to flow through the first source-drain path of the actuated first selection circuit/transistor and the corresponding write digit line to write data into certain memory elements in that row.Type: ApplicationFiled: June 23, 2005Publication date: December 22, 2005Inventors: Cyrille Dray, Christophe Frey, Jean Lasseuguette, Sebastien Barasinski, Richard Fournel
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Publication number: 20050281090Abstract: A memory device includes at least one segmented writing line formed by at least one writing segment. A programming circuit is controlled by a line address circuit in a writing mode of the memory device to program at least one memory cell coupled to the segmented writing line. A reading bit line is connected to a reading circuit for reading the contents of the cell in a reading mode of the memory device. The reading bit line cooperates in writing mode with the line address circuit to control the programming circuit of the segmented writing line.Type: ApplicationFiled: June 14, 2005Publication date: December 22, 2005Applicant: STMicroelectronics S.A.Inventors: Cyrille Dray, Sebastien Barasinski, Jean Lasseuguette, Christophe Frey, Richard Fournel