Abstract: An integrated circuit package includes an integrated circuit die. The integrated circuit die includes core circuitry implemented in one or more layers of semiconductor material, a first cluster of first contact pads formed of a top metal layer of the integrated circuit die and coupled to the core circuitry, a second cluster of second contact pads formed of the top metal layer and coupled to the core circuitry, a first ESD protection line formed of the top metal layer extending between an area of the first cluster and an area of the second cluster, and ESD protection circuitry in the one or more layers of semiconductor material coupling each of the first contact pads and each of the second contact pads to the first ESD protection line by ESD protection circuitry. The integrated circuit package includes a passivation layer on the integrated circuit die and a second ESD protection line on the passivation layer formed of a redistribution metal layer and shorting a portion of the first ESD protection line.

Abstract: A method includes a) counting whole periods of a signal during a first period of a reference signal, b) repeating step a) for each period of the reference signal until a first duration is equal to a first quantity of periods of the reference signal, and c) determining a first average of the whole periods. The method also includes repeating at least one of steps a) to c) and at each repetition shifting a start of the counting of step a) by at least one period of the reference signal, and in steps b) and c) accounting for whole periods of the signal already counted during the at least one preceding group of steps a) and b). The method includes determining a second average of the first averages, and determining the frequency of the signal from the second average and the frequency of the reference signal.

Abstract: A method includes a) counting whole periods of a signal during a first period of a reference signal, b) repeating step a) for each period of the reference signal until a first duration is equal to a first quantity of periods of the reference signal, and c) determining a first average of the whole periods. The method also includes repeating at least one of steps a) to c) and at each repetition shifting a start of the counting of step a) by at least one period of the reference signal, and in steps b) and c) accounting for whole periods of the signal already counted during the at least one preceding group of steps a) and b). The method includes determining a second average of the first averages, and determining the frequency of the signal from the second average and the frequency of the reference signal.

Abstract: A method includes a) counting whole periods of a signal during a first period of a reference signal, b) repeating step a) for each period of the reference signal until a first duration is equal to a first quantity of periods of the reference signal, and c) determining a first average of the whole periods. The method also includes repeating at least one of steps a) to c) and at each repetition shifting a start of the counting of step a) by at least one period of the reference signal, and in steps b) and c) accounting for whole periods of the signal already counted during the at least one preceding group of steps a) and b). The method includes determining a second average of the first averages, and determining the frequency of the signal from the second average and the frequency of the reference signal.

Abstract: In some embodiments, a phase locked loop includes a voltage-controlled oscillator whose output is fed back to a first input of a phase comparator via a fractional divider controlled by a delta-sigma modulator. The method of doubling the frequency of the initial reference signal of the phase locked loop involves generating, from the initial reference signal and the output signal furnished by the voltage-controlled oscillator, a secondary reference signal having edges of a first type synchronized with each of the rising and falling edges of the initial reference signal and edges of a second type between the edges of the first type, and a furnishing of the secondary reference signal at a second input of the phase comparator operating on the edges of the first type.

Abstract: In some embodiments, a phase locked loop includes a voltage-controlled oscillator whose output is fed back to a first input of a phase comparator via a fractional divider controlled by a delta-sigma modulator. The method of doubling the frequency of the initial reference signal of the phase locked loop involves generating, from the initial reference signal and the output signal furnished by the voltage-controlled oscillator, a secondary reference signal having edges of a first type synchronized with each of the rising and falling edges of the initial reference signal and edges of a second type between the edges of the first type, and a furnishing of the secondary reference signal at a second input of the phase comparator operating on the edges of the first type.

Abstract: A method can be used for contactless communication of an object with a reader using active load modulation. A main clock signal is generated within the object. The generating includes a calibration phase and a transmission phase. The calibration phase includes locking an output signal of a controlled main oscillator onto a phase and frequency of a secondary clock signal received from the reader and estimating a frequency ratio between a frequency of the output signal of the main oscillator and a reference frequency of a reference signal originating from a reference oscillator. The transmission phase includes only frequency-locking the output signal of the main oscillator onto the frequency of the reference signal corrected by the estimated frequency ratio.

Abstract: A method can be used for contactless communication of an object with a reader using active load modulation. A main clock signal is generated within the object. The generating includes a calibration phase and a transmission phase. The calibration phase includes locking an output signal of a controlled main oscillator onto a phase and frequency of a secondary clock signal received from the reader and estimating a frequency ratio between a frequency of the output signal of the main oscillator and a reference frequency of a reference signal originating from a reference oscillator. The transmission phase includes only frequency-locking the output signal of the main oscillator onto the frequency of the reference signal corrected by the estimated frequency ratio.

Abstract: A method includes a) counting whole periods of a signal during a first period of a reference signal, b) repeating step a) for each period of the reference signal until a first duration is equal to a first quantity of periods of the reference signal, and c) determining a first average of the whole periods. The method also includes repeating at least one of steps a) to c) and at each repetition shifting a start of the counting of step a) by at least one period of the reference signal, and in steps b) and c) accounting for whole periods of the signal already counted during the at least one preceding group of steps a) and b). The method includes determining a second average of the first averages, and determining the frequency of the signal from the second average and the frequency of the reference signal.

Abstract: A multiple phase oscillator includes a master oscillator that injection locks a first ring oscillator. The free-running frequency of the first ring oscillator is adjustable through a control signal. A second ring oscillator has a same structure as the first ring oscillator and is connected to operate in a free-running mode. The free-running frequency of the second ring oscillator is adjustable through the control signal. A control loop senses the output of the second ring oscillator and adjusts the control signal so that the free-running frequency of the second ring oscillator matches a desired value.

Abstract: An oscillator (200, 300, 350) comprises a tank circuit (100), a first transistor (M1c) and a second transistor (M1r), and the second transistor (M1r) occupies an area of silicon that is smaller than an area of silicon occupied by the first transistor (M1c). A switching apparatus (Sw1 . . . Sw14) selects either one of a first oscillator topology and a second oscillator topology, where in the first oscillator topology, the tank circuit (100) is coupled to the first transistor (M1c) in a first feedback configuration to provide feedback around the first transistor (M1c), and in the second oscillator topology, the tank circuit (100) is coupled to the second transistor (M1r) in a second feedback configuration that is different to the first feedback configuration to provide feedback around the second transistor (M1r).

Abstract: An oscillator (200, 300, 350) comprises a tank circuit (100), a first transistor (M1c) and a second transistor (M1r), and the second transistor (M1r) occupies an area of silicon that is smaller than an area of silicon occupied by the first transistor (M1c). A switching apparatus (Sw1 . . . Sw14) selects either one of a first oscillator topology and a second oscillator topology, where in the first oscillator topology, the tank circuit (100) is coupled to the first transistor (M1c) in a first feedback configuration to provide feedback around the first transistor (M1c), and in the second oscillator topology, the tank circuit (100) is coupled to the second transistor (M1r) in a second feedback configuration that is different to the first feedback configuration to provide feedback around the second transistor (M1r).

Abstract: A phase-locked loop circuit having a comparator that receives a target digital word representative of a non-integer target ratio between a main signal and a reference signal having a reference frequency. The circuit also includes digitally-controlled oscillator coupled to the comparator to deliver an output signal. One return loop is coupled between the output of the oscillator and the comparator. The latter includes a device to generate a digital word representing the non-integer ratio between the period of the reference signal and the period of the output signal, the reference signal and the output signal respectively corresponding to the first and second signal, and the fixed integer part N being equal to the integer part of the target non-integer ratio. The comparator compares the digital word and target digital word. The oscillator adjusts the frequency of the output signal as a function of the result delivered by the comparator.

Abstract: A method in accordance with the invention may include a cyclical succession of measurement phases and of correction phases. The correction phase may include a deactivation of a frequency divider and a correction of the control of an oscillator on the basis of the error signal, with the output signal from the oscillator forming the desired signal.

Abstract: An electronic circuit element has two capacitance values selected by means of a main control signal. The electronic circuit element comprises two variable-capacitance electronic components connected in parallel and each receiving opposite intermediate control signals, derived from the main control signal. The two variable-capacitance components are differentiated by a configuration parameter. The electronic circuit element exhibits a variation in capacitance corresponding to a difference between respective variations in capacitance of the two variable-capacitance electronic components during an inversion of the main control signal. The variation in capacitance of the electronic circuit element may be less than 5 attoFarads.

Abstract: A phase-locked loop circuit having a comparator that receives a target digital word representative of a non-integer target ratio between a main signal and a reference signal having a reference frequency. The circuit also includes digitally-controlled oscillator coupled to the comparator to deliver an output signal. One return loop is coupled between the output of the oscillator and the comparator. The latter includes a device to generate a digital word representing the non-integer ratio between the period of the reference signal and the period of the output signal, the reference signal and the output signal respectively corresponding to the first and second signal, and the fixed integer part N being equal to the integer part of the target non-integer ratio. The comparator compares the digital word and target digital word. The oscillator adjusts the frequency of the output signal as a function of the result delivered by the comparator.

Abstract: A method for correcting the phase difference between two input signals of a phase-locked loop may include a charge pump connected to a filter. Prior to the occurrence of the first of the two input signals, a calibration phase may be carried out in which the input of the filter is disconnected from the output of the charge pump, the output voltage from the charge pump is equalized, to within a given error, with the input voltage of the filter, the amplitudes of the opposing currents flowing in the charge pump being equalized. Then, during the two respective occurrences of the two input signals, the input of the filter is reconnected to the output of the charge pump, and two phase-shifted signals that are delayed with respect to the input signals are respectively generated, in response to which the two opposing currents are, respectively and successively, interrupted, before the calibration phase is recommenced.

Abstract: An electronic circuit element has two capacitance values selected by means of a main control signal. The electronic circuit element comprises two variable-capacitance electronic components connected in parallel and each receiving opposite intermediate control signals, derived from the main control signal. The two variable-capacitance components are differentiated by a configuration parameter. The electronic circuit element exhibits a variation in capacitance corresponding to a difference between respective variations in capacitance of the two variable-capacitance electronic components during an inversion of the main control signal. The variation in capacitance of the electronic circuit element may be less than 5 attoFarads.

Abstract: A method in accordance with the invention may include a cyclical succession of measurement phases and of correction phases. The correction phase may include a deactivation of a frequency divider and a correction of the control of an oscillator on the basis of the error signal, with the output signal from the oscillator forming the desired signal.

Abstract: A method for correcting the phase difference between two input signals of a phase-locked loop may include a charge pump connected to a filter. Prior to the occurrence of the first of the two input signals, a calibration phase may be carried out in which the input of the filter is disconnected from the output of the charge pump, the output voltage from the charge pump is equalized, to within a given error, with the input voltage of the filter, the amplitudes of the opposing currents flowing in the charge pump being equalized. Then, during the two respective occurrences of the two input signals, the input of the filter is reconnected to the output of the charge pump, and two phase-shifted signals that are delayed with respect to the input signals are respectively generated, in response to which the two opposing currents are, respectively and successively, interrupted, before the calibration phase is recommenced.