Patents by Inventor Sébastien Delerse
Sébastien Delerse has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11494624Abstract: Systems and methods for accelerating computation of an artificial neural network (ANN) are provided. An example method comprises receiving, by processing units coupled with arithmetic units and accumulation units, a first plurality of first values and a second plurality of second values associated with one or more neurons of the ANN, generating, by the processing units, a plurality of pairs, wherein each pair of the plurality of pairs has a first value of the first plurality and a second value of the second plurality and the first value and the second value satisfy criteria, performing, by the arithmetic units, mathematical operations on pairs of the plurality of pairs to obtain results; accumulating, by the accumulation units, the results to obtain accumulated results, and determining, by the processing units and based on the accumulated results, an output of the neurons.Type: GrantFiled: May 20, 2019Date of Patent: November 8, 2022Assignee: MIPSOLOGY SASInventors: Ludovic Larzul, Sebastien Delerse
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Patent number: 11126912Abstract: Systems and methods for realigning streams of neuron outputs are provided. An example method may include generating, by a processing unit, neuron outputs including at least a first neuron output and a second neuron output, generating, by at least one further processing unit, further neuron outputs including at least a further first neuron output and a further second neuron output, receiving, by a synchronization module communicatively coupled to the processing unit and the further processing unit, the neuron outputs, wherein the neuron outputs and the further neuron outputs are received in an arbitrary order, and ordering, by the synchronization module, the first neuron output, the further first neuron output, the second neuron output and the further second neuron output according to a further order, the further order being different from the arbitrary order.Type: GrantFiled: December 10, 2019Date of Patent: September 21, 2021Assignee: MIPSOLOGY SASInventors: Sebastien Delerse, Ludovic Larzul, Benoit Chappet De Vangel, Taoufik Chouta
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Patent number: 10990525Abstract: Systems and methods for caching data in artificial neural network computations are disclosed. An example method may comprise receiving, by a communication unit, data and a logical address of the data, the data being associated with the ANN, determining, by a processing unit coupled to the communication unit and to a plurality of physical memories and based on the logical address and physical parameters of the physical memories, a physical address of a physical memory of the plurality of physical memories, and performing, by the processing unit, an operation associated with the data and the physical address. The determination of the physical address can be based on a usage count of the data in the ANN computation or a time lapse between a time the data is written to the physical memory and a time the data is used in the ANN computation.Type: GrantFiled: December 12, 2018Date of Patent: April 27, 2021Inventors: Sebastien Delerse, Benoit Chappet de Vangel, Thomas Cagnac
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Publication number: 20210117800Abstract: Systems and methods for performing multiple locally stored artificial neural network (ANN) computations are provided. An example method comprises receiving, by one or more processing units, an ANN dataset associated with at least one ANN of a plurality of ANNs; storing, by processing units, the ANN dataset in a memory coupled to the processing units; associating, by the processing units, a base address with the at least one ANN, wherein the base address is to be used to locate the ANN dataset in the memory; keeping, by the processing units, the ANN dataset in the memory; receiving, by the processing units, an input dataset and the base address; determining, by the processing units and based on the base address, a location of the ANN dataset in the memory; and performing, by the processing units, ANN computation using the ANN dataset and input dataset.Type: ApplicationFiled: October 22, 2019Publication date: April 22, 2021Inventors: Stephane Ladevie, Ludovic Larzul, Sebastien Delerse, Frederic Dumoulin
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Publication number: 20200372328Abstract: Systems and methods for accelerating computation of an artificial neural network (ANN) are provided. An example method comprises receiving, by processing units coupled with arithmetic units and accumulation units, a first plurality of first values and a second plurality of second values associated with one or more neurons of the ANN, generating, by the processing units, a plurality of pairs, wherein each pair of the plurality of pairs has a first value of the first plurality and a second value of the second plurality and the first value and the second value satisfy criteria, performing, by the arithmetic units, mathematical operations on pairs of the plurality of pairs to obtain results; accumulating, by the accumulation units, the results to obtain accumulated results, and determining, by the processing units and based on the accumulated results, an output of the neurons.Type: ApplicationFiled: May 20, 2019Publication date: November 26, 2020Inventors: Ludovic Larzul, Sebastien Delerse
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Patent number: 10769527Abstract: Systems and methods for accelerating artificial neural network computation are disclosed. An example may comprise selecting, by a controller communicatively coupled to a selector and an arithmetic unit and based on a criterion, an input value from the stream of input values of a neuron, configuring, by the controller, the selector to provide, dynamically, the selected input value to the arithmetic unit, providing, by the controller to the arithmetic unit, an information of the selected input value, acquiring, by the arithmetic unit and based on the information, a weight from a set of weights, and performing, by the arithmetic unit a mathematical operation on the selected input value and the weight to obtain a result, wherein the result is to be used to compute an output of the neuron. The criterion may include a comparison between the input value and a reference value. The reference value may include zero.Type: GrantFiled: December 11, 2018Date of Patent: September 8, 2020Assignee: Mipsology SASInventors: Sebastien Delerse, Ludovic Larzul, Benoit Chappet de Vangel, Taoufik Chouta
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Publication number: 20200192797Abstract: Systems and methods for caching data in artificial neural network computations are disclosed. An example method may comprise receiving, by a communication unit, data and a logical address of the data, the data being associated with the ANN, determining, by a processing unit coupled to the communication unit and to a plurality of physical memories and based on the logical address and physical parameters of the physical memories, a physical address of a physical memory of the plurality of physical memories, and performing, by the processing unit, an operation associated with the data and the physical address. The determination of the physical address can be based on a usage count of the data in the ANN computation or a time lapse between a time the data is written to the physical memory and a time the data is used in the ANN computation.Type: ApplicationFiled: December 12, 2018Publication date: June 18, 2020Inventors: Sebastien Delerse, Benoit Chappet de Vangel, Thomas Cagnac
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Publication number: 20200184322Abstract: Systems and methods for realigning streams of neuron outputs are provided. An example method may include generating, by a processing unit, neuron outputs including at least a first neuron output and a second neuron output, generating, by at least one further processing unit, further neuron outputs including at least a further first neuron output and a further second neuron output, receiving, by a synchronization module communicatively coupled to the processing unit and the further processing unit, the neuron outputs, wherein the neuron outputs and the further neuron outputs are received in an arbitrary order, and ordering, by the synchronization module, the first neuron output, the further first neuron output, the second neuron output and the further second neuron output according to a further order, the further order being different from the arbitrary order.Type: ApplicationFiled: December 10, 2019Publication date: June 11, 2020Inventors: Sebastien Delerse, Ludovic Larzul, Benoit Chappet De Vangel, Taoufik Chouta
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Publication number: 20200184328Abstract: Systems and methods for accelerating artificial neural network computation are disclosed. An example may comprise selecting, by a controller communicatively coupled to a selector and an arithmetic unit and based on a criterion, an input value from the stream of input values of a neuron, configuring, by the controller, the selector to provide, dynamically, the selected input value to the arithmetic unit, providing, by the controller to the arithmetic unit, an information of the selected input value, acquiring, by the arithmetic unit and based on the information, a weight from a set of weights, and performing, by the arithmetic unit a mathematical operation on the selected input value and the weight to obtain a result, wherein the result is to be used to compute an output of the neuron. The criterion may include a comparison between the input value and a reference value. The reference value may include zero.Type: ApplicationFiled: December 11, 2018Publication date: June 11, 2020Inventors: Sebastien Delerse, Ludovic Larzul, Benoit Chappet de Vangel, Taoufik Chouta
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Patent number: 9996645Abstract: A hardware verification system according to one embodiment includes, in part, a plurality of programmable devices. The plurality of programmable devices include a master scheduler, a plurality of schedulers and a plurality of programmable delay elements. A first one of the plurality of schedulers is configured to receive one or more delay values associated with one or more of the plurality of delay elements. Each of the plurality of programmable delay elements corresponds to a delay. The first scheduler is further configured to send a parameter corresponding to the one or more delay values to the master scheduler, and generate one or more signals corresponding to the one or more delay elements in response to a control signal the first scheduler receives from the master scheduler.Type: GrantFiled: April 6, 2015Date of Patent: June 12, 2018Assignee: SYNOPSYS, INC.Inventors: Alexander Rabinovitch, Cedric Alquier, Sebastien Delerse
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Publication number: 20160292334Abstract: A hardware verification system according to one embodiment includes, in part, a plurality of programmable devices. The plurality of programmable devices include a master scheduler, a plurality of schedulers and a plurality of programmable delay elements. A first one of the plurality of schedulers is configured to receive one or more delay values associated with one or more of the plurality of delay elements. Each of the plurality of programmable delay elements corresponds to a delay. The first scheduler is further configured to send a parameter corresponding to the one or more delay values to the master scheduler, and generate one or more signals corresponding to the one or more delay elements in response to a control signal the first scheduler receives from the master scheduler.Type: ApplicationFiled: April 6, 2015Publication date: October 6, 2016Inventors: Alexander RABINOVITCH, Cedric Alquier, Sebastien Delerse
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Publication number: 20100161306Abstract: The method of emulating the design under test associated with a test environment comprises two distinct generating phases comprising a first phase of generating (80) a first file (FCH1) for configuring the test environment, and a second phase of generating (81) a second file (FCH2) for configuring at least a part of the design under test, the delivery of the first configuration file to a first reconfigurable hardware part (BTR) forming a reconfigurable test bench so as to configure the test bench, and the delivery of the second configuration file to a second reconfigurable hardware part (EML) so as to configure an emulator of the design under test, the two hardware parts being distinct and mutually connected.Type: ApplicationFiled: July 22, 2009Publication date: June 24, 2010Applicant: EMULATION AND VERIFICATION ENGINEERINGInventors: LUC BURGUN, DAVID REYNIER, Sébastien Delerse, Frédéric Emirian, FRANCOIS DOUËZY
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Publication number: 20040111252Abstract: The method of emulating the design under test associated with a test environment comprises two distinct generating phases comprising a first phase of generating (80) a first file (FCH1) for configuring the test environment, and a second phase of generating (81) a second file (FCH2) for configuring at least a part of the design under test, the delivery of the first configuration file to a first reconfigurable hardware part (BTR) forming a reconfigurable test bench so as to configure the test bench, and the delivery of the second configuration file to a second reconfigurable hardware part (EML) so as to configure an emulator of the design under test, the two hardware parts being distinct and mutually connected.Type: ApplicationFiled: June 26, 2003Publication date: June 10, 2004Applicant: EMULATION AND VERIFICATION ENGINEERINGInventors: Luc Burgun, David Reynier, Sebastien Delerse, Frederic Emirian, Francois Douezy