Patents by Inventor Sébastien Desplobain

Sébastien Desplobain has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8470689
    Abstract: The method for forming a multilayer structure on a substrate comprises providing a stack successively comprising an electron hole blocking layer, a first layer made from N-doped semiconductor material having a dopant concentration greater than or equal to 1018 atoms/cm3 or P-doped semiconductor material, and a second layer made from semiconductor material of different nature. A lateral electric contact pad is made between the first layer and the substrate, and the material of the first layer is subjected to anodic treatment in an electrolyte.
    Type: Grant
    Filed: November 10, 2011
    Date of Patent: June 25, 2013
    Assignees: Commissariat a l'Energie Atomique et aux Energies Alternatives, STMicroelectronics (Crolles 2) SAS
    Inventors: Sébastien Desplobain, Frederic-Xavier Gaillard, Yves Morand, Fabrice Nemouchi
  • Publication number: 20120115311
    Abstract: The method for forming a multilayer structure on a substrate comprises providing a stack successively comprising an electron hole blocking layer, a first layer made from N-doped semiconductor material having a dopant concentration greater than or equal to 1018 atoms/cm3or P-doped semiconductor material, and a second layer made from semiconductor material of different nature. A lateral electric contact pad is made between the first layer and the substrate, and the material of the first layer is subjected to anodic treatment in an electrolyte.
    Type: Application
    Filed: November 10, 2011
    Publication date: May 10, 2012
    Applicants: STMICROELECTRONICS (CROLLES 2) SAS, COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Sébastien DESPLOBAIN, Frederic-Xavier GAILLARD, Yves MORAND, Fabrice NEMOUCHI
  • Publication number: 20110053053
    Abstract: A porous silicon wafer including, on its upper surface side, multiple recesses, this upper surface being coated with a porous silicon layer having pores smaller than those of the wafer bulk.
    Type: Application
    Filed: September 18, 2008
    Publication date: March 3, 2011
    Applicant: STMicroelectronics S.A.
    Inventors: Sébastien Desplobain, Gaël Gautier