Patents by Inventor Sébastien Jouan
Sébastien Jouan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9985119Abstract: An integrated image sensor may include adjacent pixels, with each pixel including an active semiconductor region including a photodiode, an antireflection layer disposed above the photodiode, a dielectric region disposed above the antireflection layer, an optical filter disposed above the dielectric region, and a diffraction grating disposed in the antireflection layer. The diffraction grating includes an array of pads.Type: GrantFiled: April 17, 2017Date of Patent: May 29, 2018Assignees: STMICROELECTRONICS S.A., STMICROELECTRONICS (Crolles 2) SASInventors: Axel Crocherie, Michel Marty, Jean-Luc Huguenin, Sébastien Jouan
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Publication number: 20170221948Abstract: An integrated image sensor may include adjacent pixels, with each pixel including an active semiconductor region including a photodiode, an antireflection layer disposed above the photodiode, a dielectric region disposed above the antireflection layer, an optical filter disposed above the dielectric region, and a diffraction grating disposed in the antireflection layer. The diffraction grating includes an array of pads.Type: ApplicationFiled: April 17, 2017Publication date: August 3, 2017Inventors: Axel Crocherie, Michel Marty, Jean-Luc Huguenin, Sébastien Jouan
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Patent number: 9685472Abstract: An integrated image sensor may include adjacent pixels, with each pixel including an active semiconductor region including a photodiode, an antireflection layer above the photodiode, a dielectric region above the antireflection layer and an optical filter to pass incident luminous radiation having a given wavelength. The antireflection layer may include an array of pads mutually separated by a dielectric material of the dielectric region. The array may be configured to allow simultaneous transmission of the incident luminous radiation and a diffraction of the incident luminous radiation producing diffracted radiations which have wavelengths below that of the incident radiation, and are attenuated with respect to the incident radiation.Type: GrantFiled: February 23, 2016Date of Patent: June 20, 2017Assignees: STMICROELECTRONICS SA, STMICROELECTRONICS (CROLLES 2) SASInventors: Axel Crocherie, Michel Marty, Jean-Luc Huguenin, Sébastien Jouan
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Publication number: 20170062507Abstract: An integrated image sensor may include adjacent pixels, with each pixel including an active semiconductor region including a photodiode, an antireflection layer above the photodiode, a dielectric region above the antireflection layer and an optical filter to pass incident luminous radiation having a given wavelength. The antireflection layer may include an array of pads mutually separated by a dielectric material of the dielectric region. The array may be configured to allow simultaneous transmission of the incident luminous radiation and a diffraction of the incident luminous radiation producing diffracted radiations which have wavelengths below that of the incident radiation, and are attenuated with respect to the incident radiation.Type: ApplicationFiled: February 23, 2016Publication date: March 2, 2017Inventors: Axel CROCHERIE, Michel MARTY, Jean-Luc HUGUENIN, Sébastien JOUAN
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Patent number: 9450000Abstract: A photodiode includes at least one central pad arranged on a light-receiving surface of a photodiode semiconductor substrate. The pad is made of a first material and includes lateral sidewalls surrounded by a spacer made of a second material having a different optical index than the first material. The lateral dimensions of the pad are smaller than an operating wavelength of the photodiode. Both the first and second materials are transparent to that operating wavelength. The pads and spacers are formed at a same time gate electrodes and sidewall spacers of MOS transistors are formed.Type: GrantFiled: August 19, 2014Date of Patent: September 20, 2016Assignees: STMicroelectronics (Crolles 2) SAS, STMicroelectronics SA, Commissariat A L'Energie Atomique et aux Energies AlternativesInventors: Michel Marty, Sebastien Jouan, Laurent Frey, Salim Boutami
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Patent number: 9299865Abstract: A SPAD-type photodiode has a semiconductor substrate with a light-receiving surface. A lattice formed of interlaced strips made of a first material covers the light receiving surface. The lattice includes lattice openings with lateral walls covered by a spacer made of a second material. Then first and second materials have different optical indices, and further each optical index is less than or equal to the substrate optical index. A pitch of the lattice is of the order of a magnitude of an operating wavelength of the photodiode. The first and second materials are transparent at that operating wavelength. The lattice is made of a conductive material electrically coupled to an electrical connection node (for example, a bias voltage node).Type: GrantFiled: August 21, 2014Date of Patent: March 29, 2016Assignees: STMicroelectronics (Crolles 2) SAS; STMicroelectronics SA, Commissariat A L'Energie Atomique et aux Energies AlternativesInventors: Michel Marty, Laurent Frey, Sebastien Jouan, Salim Boutami
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Patent number: 9219095Abstract: An integrated circuit includes a substrate and an interconnect part above the substrate, and further includes a photosensitive region in the substrate. A filter is provided aligned with the photosensitive region. The filter is formed by at least one layer of filter material. In one implementation for front side illumination, the layer of filter material is positioned above the photosensitive region between the interconnect part and the substrate. In another implementation for back side illumination, the layer of filter material is positioned below the photosensitive region opposite the interconnect part. The layer of filter material is configured such that a product of the thickness of the layer of filter material and the imaginary part of the refractive index of the layer of filter material is above 1 nm.Type: GrantFiled: September 18, 2014Date of Patent: December 22, 2015Assignees: STMicroelectronics SA, STMicroelectronics (Crolles 2) SAS, Commissariat A L'Energie Atomique et aux Energies AlternativesInventors: Michel Marty, Sebastien Jouan, Laurent Frey
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Publication number: 20150076573Abstract: An integrated circuit includes a substrate and an interconnect part above the substrate, and further includes a photosensitive region in the substrate. A filter is provided aligned with the photosensitive region. The filter is formed by at least one layer of filter material. In one implementation for front side illumination, the layer of filter material is positioned above the photosensitive region between the interconnect part and the substrate. In another implementation for back side illumination, the layer of filter material is positioned below the photosensitive region opposite the interconnect part. The layer of filter material is configured such that a product of the thickness of the layer of filter material and the imaginary part of the refractive index of the layer of filter material is above 1 nm.Type: ApplicationFiled: September 18, 2014Publication date: March 19, 2015Applicants: STMicroelectronics SA, STMicroelectronics (Crolles 2) SAS, Commissariat A L'Energie Atomique et aux Energies AlternativesInventors: Michel Marty, Sebastien Jouan, Laurent Frey
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Patent number: 8975730Abstract: A device and corresponding fabrication method includes a vertical stack having an intermediate layer between a lower region and an upper region. The intermediate layer is extended by a protection layer. The vertical stack has a free lateral face on which the lower region, the upper region and the protection layer are exposed.Type: GrantFiled: September 19, 2012Date of Patent: March 10, 2015Assignees: STMicroelectronics (Crolles 2) SAS, STMicroelectronics SAInventors: Didier Dutartre, Michel Marty, Sebastien Jouan
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Publication number: 20150054042Abstract: A photodiode includes at least one central pad arranged on a light-receiving surface of a photodiode semiconductor substrate. The pad is made of a first material and includes lateral sidewalls surrounded by a spacer made of a second material having a different optical index than the first material. The lateral dimensions of the pad are smaller than an operating wavelength of the photodiode. Both the first and second materials are transparent to that operating wavelength. The pads and spacers are formed at a same time gate electrodes and sidewall spacers of MOS transistors are formed.Type: ApplicationFiled: August 19, 2014Publication date: February 26, 2015Applicants: STMicroelectronics (Crolles 2) SAS, STMicroelectronics SA, Commissariat A L'Energie Atomique et aux Energies AlternativesInventors: Michel Marty, Sebastien Jouan, Laurent Frey, Salim Boutami
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Publication number: 20150053924Abstract: A SPAD-type photodiode has a semiconductor substrate with a light-receiving surface. A lattice formed of interlaced strips made of a first material covers the light receiving surface. The lattice includes lattice openings with lateral walls covered by a spacer made of a second material. Then first and second materials have different optical indices, and further each optical index is less than or equal to the substrate optical index. A pitch of the lattice is of the order of a magnitude of an operating wavelength of the photodiode. The first and second materials are transparent at that operating wavelength. The lattice is made of a conductive material electrically coupled to an electrical connection node (for example, a bias voltage node).Type: ApplicationFiled: August 21, 2014Publication date: February 26, 2015Applicants: STMicroelectronics (Crolles 2) SAS, STMicroelectronics SA, Commissariat A L'Energie Atomique et aux Energies AlternativesInventors: Michel Marty, Laurent Frey, Sebastien Jouan, Salim Boutami
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Patent number: 7470559Abstract: A method for forming a buried mirror in a semiconductor component includes the steps of forming a structure comprising a semiconductor layer laid on an insulating layer covering a substrate; forming one or several openings in the semiconductor layer emerging at the surface of the insulating layer; eliminating a portion of the insulating layer, whereby a recess is formed; forming a second thin insulating layer against the wall of the recess; and forming a metal layer in the recess against the second insulating layer.Type: GrantFiled: December 8, 2005Date of Patent: December 30, 2008Assignees: STMicroelectronics SA, STMicroelectronics (Canada) Inc.Inventors: Sébastien Jouan, Michel Marty
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Publication number: 20080272418Abstract: A method for forming a buried mirror in a semiconductor component includes the steps of forming a structure comprising a semiconductor layer laid on an insulating layer covering a substrate; forming one or several openings in the semiconductor layer emerging at the surface of the insulating layer; eliminating a portion of the insulating layer, whereby a recess is formed; forming a second thin insulating layer against the wall of the recess; and forming a metal layer in the recess against the second insulating layer.Type: ApplicationFiled: May 1, 2008Publication date: November 6, 2008Applicants: STMicroelectronics SA, STMicroelectronics (Canada) Inc.Inventors: Sebastien Jouan, Michel Marty
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Publication number: 20060118897Abstract: A method for forming a buried mirror in a semiconductor component includes the steps of forming a structure comprising a semiconductor layer laid on an insulating layer covering a substrate; forming one or several openings in the semiconductor layer emerging at the surface of the insulating layer; eliminating a portion of the insulating layer, whereby a recess is formed; forming a second thin insulating layer against the wall of the recess; and forming a metal layer in the recess against the second insulating layer.Type: ApplicationFiled: December 8, 2005Publication date: June 8, 2006Inventors: Sebastien Jouan, Michel Marty
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Patent number: 6656812Abstract: A vertical bipolar transistor includes a semiconductor substrate, an extrinsic collector layer in the semiconductor substrate, an intrinsic collector on the extrinsic collector, a lateral isolating region surrounding an upper part of the intrinsic collector, an offset extrinsic collector well, a base including a semiconductor region above the intrinsic collector and above the lateral isolating region including at least one silicon layer, and a doped emitter surrounded by the base. The doped emitter may include first and second parts. The first part may be formed from single-crystal silicon and in direct contact with the upper surface of the semiconductor region in a predetermined window in the upper surface above the intrinsic collector. The second part may be formed from polycrystalline silicon. The two parts of the emitter may be separated by a separating oxide layer spaced apart from the emitter-base junction of the transistor.Type: GrantFiled: November 21, 2000Date of Patent: December 2, 2003Assignee: STMicroelectronics SAInventors: Michel Marty, Didier Dutartre, Alain Chantre, Sébastien Jouan, Pierre Llinares
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Patent number: 6642096Abstract: A method of manufacturing a bipolar transistor in a single-crystal silicon substrate of a first conductivity type, including a step of carbon implantation at the substrate surface followed by an anneal step, before forming, by epitaxy, the transistor base in the form of a single-crystal semiconductor multilayer including at least a lower layer, a heavily-doped median layer of the second conductivity type, and an upper layer that contacts a heavily-doped emitter of the first conductivity type.Type: GrantFiled: September 5, 2001Date of Patent: November 4, 2003Assignee: STMicroelectronics S.A.Inventors: Didier Dutartre, Alain Chantre, Michel Marty, Sébastien Jouan
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Publication number: 20020042178Abstract: A method of manufacturing a bipolar transistor in a single-crystal silicon substrate of a first conductivity type, including a step of carbon implantation at the substrate surface followed by an anneal step, before forming, by epitaxy, the transistor base in the form of a single-crystal semiconductor multilayer including at least a lower layer, a heavily-doped median layer of the second conductivity type, and an upper layer that contacts a heavily-doped emitter of the first conductivity type.Type: ApplicationFiled: September 5, 2001Publication date: April 11, 2002Inventors: Didier Dutartre, Alain Chantre, Michel Marty, Sebastien Jouan