Patents by Inventor Sébastien Laville
Sébastien Laville has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8346982Abstract: A switch for switching video signals in a set top box between a first interface for connecting the set top box to a television, a second interface for connecting the set top box to a video playback device, and decoding circuitry for decoding a video stream, the set top box including a processor having a low power mode in which the decoding circuitry is inactive, the switch including detection circuitry arranged to detect, while the processor is in the low power mode, activity on a video input line of one of the first and second interfaces, and arranged to output an activation signal to switching circuitry in the switch to activate a loop through between the first and second interfaces when activity is detected.Type: GrantFiled: December 14, 2007Date of Patent: January 1, 2013Assignee: STMicroelectronics S.A.Inventors: Sébastien Laville, Jean-Marc Merval
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Patent number: 7999597Abstract: A circuit adjustable after packaging includes a functional circuit supplied with a power potential and a reference potential and has at least one parameter adjustable by programming at least one programmable element and a circuit to program the programmable element of the functional circuit. The adjustable circuit also includes a limiter circuit to limit the voltage between the power supply potential and the reference potential to an adjustable limiting voltage, and a circuit to adjust the limiting voltage. After adjusting a parameter of the functional circuit, the limiting voltage of the limiter circuit is adjusted.Type: GrantFiled: May 21, 2009Date of Patent: August 16, 2011Assignee: STMicroelectronics S.A.Inventors: Sébastien Laville, Frédéric Goutti
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Patent number: 7589577Abstract: A circuit adjustable after packaging includes a functional circuit supplied with a power potential and a reference potential and has at least one parameter adjustable by programming at least one programmable element and a circuit to program the programmable element of the functional circuit. The adjustable circuit also includes a limiter circuit to limit the voltage between the power supply potential and the reference potential to an adjustable limiting voltage, and a circuit to adjust the limiting voltage. After adjusting a parameter of the functional circuit, the limiting voltage of the limiter circuit is adjusted.Type: GrantFiled: December 13, 2005Date of Patent: September 15, 2009Assignee: STMicroelectronics SAInventors: Sébastien Laville, Frédéric Goutti
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Publication number: 20090224815Abstract: A circuit adjustable after packaging includes a functional circuit supplied with a power potential and a reference potential and has at least one parameter adjustable by programming at least one programmable element and a circuit to program the programmable element of the functional circuit. The adjustable circuit also includes a limiter circuit to limit the voltage between the power supply potential and the reference potential to an adjustable limiting voltage, and a circuit to adjust the limiting voltage. After adjusting a parameter of the functional circuit, the limiting voltage of the limiter circuit is adjusted.Type: ApplicationFiled: May 21, 2009Publication date: September 10, 2009Applicant: STMicroelectronics S.A.Inventors: Sebastien LAVILLE, Frederic GOUTTI
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Publication number: 20080148337Abstract: A switch for switching video signals in a set top box between a first interface for connecting the set top box to a television, a second interface for connecting the set top box to a video playback device, and decoding circuitry for decoding a video stream, the set top box including a processor having a low power mode in which the decoding circuitry is inactive, the switch including detection circuitry arranged to detect, while the processor is in the low power mode, activity on a video input line of one of the first and second interfaces, and arranged to output an activation signal to switching circuitry in the switch to activate a loop through between the first and second interfaces when activity is detected.Type: ApplicationFiled: December 14, 2007Publication date: June 19, 2008Applicant: STMicroelectronics S.A.Inventors: Sebastien Laville, Jean-Marc Merval
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Publication number: 20060132992Abstract: A circuit adjustable after packaging includes a functional circuit supplied with a power potential and a reference potential and has at least one parameter adjustable by programming at least one programmable element and a circuit to program the programmable element of the functional circuit. The adjustable circuit also includes a limiter circuit to limit the voltage between the power supply potential and the reference potential to an adjustable limiting voltage, and a circuit to adjust the limiting voltage. After adjusting a parameter of the functional circuit, the limiting voltage of the limiter circuit is adjusted.Type: ApplicationFiled: December 13, 2005Publication date: June 22, 2006Inventors: Sebastien Laville, Frederic Goutti
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Patent number: 6963239Abstract: Adjustment of an operating parameter of an analog electronic circuit is effectuated through a set of adjustment resistances (22) that can be configured from outside the circuit to modulate the value of resistances (R1, R2) in the circuit and thus to adjust the value of the parameter. Fusible elements (20) each associated with one of the said adjustment resistances are selected and activated to configure the resistances of the adjustment device. A combinational logic circuit (18) receives a control signal as input applied from outside the circuit onto a terminal (C) operates to select one of the fusible elements (20) as a function of a signal applied thereto.Type: GrantFiled: July 28, 2003Date of Patent: November 8, 2005Assignee: STMicroelectronics S.A.Inventors: Sebastien Laville, Serge Pontarollo
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Patent number: 6953971Abstract: A device for adjusting an integrated circuit before encapsulation includes a first MOS transistor having a gate and a source connected together, and a body connected to a voltage reference. A first resistor is connected in parallel with the first MOS transistor. A second MOS transistor is connected in series with the first MOS transistor. The second MOS transistor has a gate and a source connected together, and a body connected to the voltage reference. A second resistor is connected in parallel with the second MOS transistor. A first terminal is connected to the source of the first MOS transistor, and a second terminal is connected to the source of the second MOS transistor. The first terminal is accessible externally after the integrated circuit has been encapsulated.Type: GrantFiled: February 11, 2002Date of Patent: October 11, 2005Assignee: STMircoelectronics SAInventors: Sébastien Laville, Serge Pontarollo
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Publication number: 20050073350Abstract: Adjustment of an operating parameter of an analog electronic circuit is effectuated through a set of adjustment resistances (22) that can be configured from outside the circuit to modulate the value of resistances (R1, R2) in the circuit and thus to adjust the value of the parameter. Fusible elements (20) each associated with one of the said adjustment resistances are selected and activated to configure the resistances of the adjustment device. A combinational logic circuit (18) receives a control signal as input applied from outside the circuit onto a terminal (C) operates to select one of the fusible elements (20) as a function of a signal applied thereto.Type: ApplicationFiled: July 28, 2003Publication date: April 7, 2005Inventors: Sebastien Laville, Serge Pontarollo
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Publication number: 20040150049Abstract: A device for adjusting an integrated circuit before encapsulation includes a first MOS transistor having a gate and a source connected together, and a body connected to a voltage reference. A first resistor is connected in parallel with the first MOS transistor. A second MOS transistor is connected in series with the first MOS transistor. The second MOS transistor has a gate and a source connected together, and a body connected to the voltage reference. A second resistor is connected in parallel with the second MOS transistor. A first terminal is connected to the source of the first MOS transistor, and a second terminal is connected to the source of the second MOS transistor. The first terminal is acessible externally after the integrated circuit has been encapsulated.Type: ApplicationFiled: January 20, 2004Publication date: August 5, 2004Inventors: Sebastien Laville, Serge Pontarollo
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Patent number: 6653669Abstract: An integrated circuit includes an adjustment resistor, and at least one control transistor connected to a first voltage reference. An adjustment element is connected in parallel with the adjustment resistor for adjusting a combined electrical resistance of the adjustment element and the resistor. The adjustment element is connected to the control transistor, and includes a substrate, and a MOS transistor having a source, a drain, and a gate on the substrate. The MOS transistor defines a parasitic bipolar transistor with the substrate. The adjustment element further includes a first resistor connected between the substrate and the source, and a second resistor is connected between the substrate and the drain. A diode is connected in series with the second resistor between the substrate and the drain. The gate and the source of the MOS transistor are connected together with the MOS transistor being broken down so that the adjustable element forms an electrical resistance.Type: GrantFiled: April 12, 2002Date of Patent: November 25, 2003Assignee: STMicroelectronics SAInventors: Sébastien Laville, Serge Pontarollo
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Publication number: 20030022455Abstract: An integrated circuit includes an adjustment resistor, and at least one control transistor connected to a first voltage reference. An adjustment element is connected in parallel with the adjustment resistor for adjusting a combined electrical resistance of the adjustment element and the resistor. The adjustment element is connected to the control transistor, and includes a substrate, and a MOS transistor having a source, a drain, and a gate on the substrate. The MOS transistor defines a parasitic bipolar transistor with the substrate. The adjustment element further includes a first resistor connected between the substrate and the source, and a second resistor is connected between the substrate and the drain. A diode is connected in series with the second resistor between the substrate and the drain. The gate and the source of the MOS transistor are connected together with the MOS transistor being broken down so that the adjustable element forms an electrical resistance.Type: ApplicationFiled: April 12, 2002Publication date: January 30, 2003Applicant: STMicroelectronics S.A.Inventors: Sebastien Laville, Serge Pontarollo
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Patent number: 6410398Abstract: A process for forming an electrical resistance in an integrated MOS transistor includes applying a first voltage to the source and gate of the MOS transistor, and applying a second voltage to the drain of the MOS transistor. A prebiasing voltage is applied to the substrate of the MOS transistor to make the base/emitter junction of a parasitic bipolar transistor of the MOS transistor conduct. The first and second voltages are capable of initiating a breakdown of the MOS transistor by an avalanche of the drain/substrate junction, an irreversible breakdown of the drain/substrate junction, and a short circuit between the drain and the source.Type: GrantFiled: June 28, 2000Date of Patent: June 25, 2002Assignee: STMicroelectronics S.A.Inventors: Christophe Forel, Sebastien Laville, Serge Pontarollo
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Patent number: 6377115Abstract: A process and an integrated circuit are intended for obtaining an adjustable electrical resistance, in which a first voltage is applied to an integrated MOS transistor on its source, its gate and its substrate, and a second voltage is applied on its drain, the first and second voltages being able to initiate a breakdown of the MOS transistor by: avalanche of the drain/substrate junction; biasing of the parasitic bipolar transistor of the MOS transistor; irreversible breakdown of the drain/substrate junction; and shorting between the drain and the source.Type: GrantFiled: October 4, 2000Date of Patent: April 23, 2002Assignee: STMicroelectronics S.A.Inventors: Christophe Forel, Sebastien Laville, Christian Dufaza, Daniel Auvergne