Abstract: A method of programming a FPGA, wherein the FPGA comprises an array of macrocells, each comprising at least a configurable hardware block and a configurable interconnection network, the method comprises the steps of: providing a high-level configuration file containing: first data defining a set of macrocells and their relative positions; second data defining a configuration of the hardware blocks of the macrocells; and third data defining interconnections between the macrocells; wherein said high-level configuration file contains neither data defining an absolute position of the macrocells within the FPGA, nor local routing information fully defining a configuration of their interconnection networks; converting said high-level configuration file into a bitstream file; and uploading the bitstream file into the FPGA. A semiconductor chip comprising a FPGA and a device configured for programming the FPGA are provided.

Abstract: The invention relates to a method for determining by optimization a multi-core architecture and a way of implementing an application on the architecture for a given application, the method comprising: providing a parallelized application and candidate architectures comprising different hardware blocks, defining a first exploration space whose elements are the different ways of implementing the application on each of the candidate architectures, selecting, in the first exploration space, the elements verifying a criterion to obtain a second exploration space, determining, in the second exploration space, the elements verifying a criterion to obtain a third exploration space, computing the number of data exchanged between the hardware blocks for each of the elements of the third exploration space to obtain a fourth exploration space, and optimizing the elements of the fourth exploration space according to a criterion.

Abstract: A method of programming a FPGA, wherein the FPGA comprises an array of macrocells, each comprising at least a configurable hardware block and a configurable interconnection network, the method comprises the steps of: providing a high-level configuration file containing: first data defining a set of macrocells and their relative positions; second data defining a configuration of the hardware blocks of the macrocells; and third data defining interconnections between the macrocells; wherein said high-level configuration file contains neither data defining an absolute position of the macrocells within the FPGA, nor local routing information fully defining a configuration of their interconnection networks; converting said high-level configuration file into a bitstream file; and uploading the bitstream file into the FPGA. A semiconductor chip comprising a FPGA and a device configured for programming the FPGA are provided.

Abstract: The invention relates to a method for determining by optimization a multi-core architecture and a way of implementing an application on the architecture for a given application, the method comprising: providing a parallelized application and candidate architectures comprising different hardware blocks, defining a first exploration space whose elements are the different ways of implementing the application on each of the candidate architectures, selecting, in the first exploration space, the elements verifying a criterion to obtain a second exploration space, determining, in the second exploration space, the elements verifying a criterion to obtain a third exploration space, computing the number of data exchanged between the hardware blocks for each of the elements of the third exploration space to obtain a fourth exploration space, and optimizing the elements of the fourth exploration space according to a criterion.