Patents by Inventor Sébastien Rieubon
Sébastien Rieubon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 8766683Abstract: According to embodiments, dual path loop filter circuits are described which have, for example, a single charge pump. The current flow in the DPLF circuit is architected to source, during an injection time period, a first current to the loop filter, sink, also during the injection time period, a second current from the loop filter, wherein the first current has a magnitude of ?*I and the second current has a magnitude of ?*I, and sink, during a linearization time period, a third current from the loop filter, wherein the third current has a magnitude of (???)*I.Type: GrantFiled: July 19, 2013Date of Patent: July 1, 2014Assignee: ST-Ericsson SAInventors: Marc Houdebine, Julien Kieffer, Sebastien Rieubon
-
Publication number: 20140049304Abstract: According to embodiments, dual path loop filter circuits are described which have, for example, a single charge pump. The current flow in the DPLF circuit is architected to source, during an injection time period, a first current to the loop filter, sink, also during the injection time period, a second current from the loop filter, wherein the first current has a magnitude of ?*I and the second current has a magnitude of ?*I, and sink, during a linearization time period, a third current from the loop filter, wherein the third current has a magnitude of (???)*I.Type: ApplicationFiled: July 19, 2013Publication date: February 20, 2014Applicant: ST-Ericsson SAInventors: Marc HOUDEBINE, Julien KIEFFER, Sebastien RIEUBON
-
Patent number: 8531245Abstract: A method and apparatus for compensating for temperature variation in a phase locked loop (PLL) includes receiving an error signal by a controller in which the error signal representative of an instantaneous frequency difference between a reference frequency signal and an output frequency signal of a voltage controlled oscillator of the PLL, and determining when a voltage of the error signal is outside of a predetermined voltage range. When the voltage is outside the predetermined voltage range, the method includes generating a new digital compensation signal based upon a previous digital compensation signal, and converting the new digital compensation signal to be an analog compensation signal. The method further includes filtering the analog compensation signal by a filter to produce a filtered analog compensation signal, and adjusting the output frequency of the voltage controlled oscillator in accordance with the filtered analog compensation signal.Type: GrantFiled: October 28, 2011Date of Patent: September 10, 2013Assignee: ST-Ericsson SAInventors: Cyril Joubert, Sebastien Rieubon
-
Publication number: 20130106476Abstract: A method and apparatus for compensating for temperature variation in a phase locked loop (PLL) includes receiving an error signal by a controller in which the error signal representative of an instantaneous frequency difference between a reference frequency signal and an output frequency signal of a voltage controlled oscillator of the PLL, and determining when a voltage of the error signal is outside of a predetermined voltage range. When the voltage is outside the predetermined voltage range, the method includes generating a new digital compensation signal based upon a previous digital compensation signal, and converting the new digital compensation signal to be an analog compensation signal. The method further includes filtering the analog compensation signal by a filter to produce a filtered analog compensation signal, and adjusting the output frequency of the voltage controlled oscillator in accordance with the filtered analog compensation signal.Type: ApplicationFiled: October 28, 2011Publication date: May 2, 2013Applicant: ST-ERICSSON SAInventors: CYRIL JOUBERT, SEBASTIEN RIEUBON
-
Publication number: 20120229185Abstract: The invention relates to the conversion into digital information of the time difference between a first signal and a second signal. In particular, in order to determine a fractional part of the number of periods of a first signal for a period of a second signal, the following are alternately performed: /1/ delaying the second signal relative to the first signal and determining a first digital information item, a function of the fractional part, /2/ delaying the first signal relative to the second signal and determining a second digital information item, a function of the fractional part. Then the fractional part is calculated as a function of the previously obtained first and second digital information items.Type: ApplicationFiled: November 12, 2010Publication date: September 13, 2012Inventor: Sébastien Rieubon
-
Patent number: 8212597Abstract: A method is for detecting locking of a phase-locked loop that generates an output signal and includes a phase comparator receiving, as an input, a reference signal and a second signal based upon the output signal. A time window having a duration of at least two periods of a third signal based upon the output signal, and located about a payload edge of the second signal, is generated. A first comparison of the reference signal and the second signal at a first payload edge of the third signal within the time window and on a first side of the payload edge of the second signal is performed. A second comparison of the reference signal and the second signal at a second payload edge of the third signal within the time window and on a second side of the payload edge of the second signal is then performed. Locking of the phase-locked loop based upon the reference signal and the second signal being equal during the first and second comparisons is detected.Type: GrantFiled: January 15, 2010Date of Patent: July 3, 2012Inventors: Michael Kraemer, Sébastien Rieubon
-
Patent number: 7821345Abstract: A method of calibrating an oscillator in order to compensate the dispersions generated, on the one hand, during the process of fabricating the oscillator circuit components and, on the other hand, by variations of operating conditions by modifying the parameters of a resonant component, for example a capacitor or an induction coil of the oscillator, in order to change the frequency range covered by the oscillator, according to the control voltage. Accordingly, calibrating the oscillator adjusts the output frequency of the oscillator according to an oscillator control signal. The calibration device determines the difference between the output frequency of the oscillator divided by a quantity and a reference frequency of the oscillator. The device includes a set of impedances selectively connected to the oscillator and each corresponding to a frequency deviation of the oscillator, and a calibration stage to generate a calibration word according to the measured frequency difference.Type: GrantFiled: January 23, 2007Date of Patent: October 26, 2010Assignee: STMicroelectronics SAInventors: Michael Kraemer, Sebastien Rieubon
-
Publication number: 20100176845Abstract: A method is for detecting locking of a phase-locked loop that generates an output signal and includes a phase comparator receiving, as an input, a reference signal and a second signal based upon the output signal. A time window having a duration of at least two periods of a third signal based upon the output signal, and located about a payload edge of the second signal, is generated. A first comparison of the reference signal and the second signal at a first payload edge of the third signal within the time window and on a first side of the payload edge of the second signal is performed. A second comparison of the reference signal and the second signal at a second payload edge of the third signal within the time window and on a second side of the payload edge of the second signal is then performed. Locking of the phase-locked loop based upon the reference signal and the second signal being equal during the first and second comparisons is detected.Type: ApplicationFiled: January 15, 2010Publication date: July 15, 2010Applicant: STMicroelectronics (Grenoble 2) SASInventors: Michael KRAEMER, Sébastien Rieubon
-
Patent number: 7466789Abstract: The invention concerns counting circuitry for providing a corrected count value based on the number of rising and falling edges of an input signal occurring during a reference time period, the counting circuitry comprising a counter (22) arranged to provide a first count value based on one of the number of said rising edges of said input signal occurring during said reference time period, and the number of said falling edges of said input signal occurring during said reference time period; characterized in that said counting circuitry further comprises adjustment circuitry (24-26) arranged to generate a corrected count value by determining the state of said input signal at the start time (70) and end time (72) of said reference time period, and adjusting said first count value if the state of said input signal at the start of said reference time period is different from the state of said input signal at the end of said reference time period.Type: GrantFiled: March 15, 2007Date of Patent: December 16, 2008Assignee: STMicroelectronics S.A.Inventors: Sébastien Rieubon, Michael Kraemer
-
Publication number: 20070216556Abstract: The invention concerns counting circuitry for providing a corrected count value based on the number of rising and falling edges of an input signal occurring during a reference time period, the counting circuitry including a counter arranged to provide a first count value based on one of the number of the rising edges of the input signal occurring during the reference time period, and the number of the falling edges of the input signal occurring during the reference time period; wherein the counting circuitry further includes adjustment circuitry arranged to generate a corrected count value by determining the state of the input signal at the start time and end time of the reference time period, and adjusting the first count value if the state of the input signal at the start of the reference time period is different from the state of the input signal at the end of the reference time period.Type: ApplicationFiled: March 15, 2007Publication date: September 20, 2007Applicant: STMicroelectronics S.A.Inventors: Sebastien Rieubon, Michael Kraemer
-
Publication number: 20070188245Abstract: A method of calibrating an oscillator in order to compensate the dispersions generated, on the one hand, during the process of fabricating the oscillator circuit components and, on the other hand, by variations of operating conditions by modifying the parameters of a resonant component, for example a capacitor or an induction coil of the oscillator, in order to change the frequency range covered by the oscillator, according to the control voltage. Accordingly, calibrating the oscillator adjusts the output frequency of the oscillator according to an oscillator control signal. The calibration device determines the difference between the output frequency of the oscillator divided by a quantity and a reference frequency of the oscillator.Type: ApplicationFiled: January 23, 2007Publication date: August 16, 2007Applicant: STMICROELECTRONICS SAInventors: Michael Kraemer, Sebastien Rieubon
-
Patent number: 7145366Abstract: An electronic circuit includes at least one differential pair of transistors, a control transistor switch, a first current source and a second current source. The second current source is connected to a common emitter node of the pair of transistors in order to accelerate the discharge of parasitic capacitances during a switching operation.Type: GrantFiled: September 30, 2004Date of Patent: December 5, 2006Assignee: STMicroelectronics S.A.Inventors: Sébastien Rieubon, Serge Ramet, Philippe Level
-
Publication number: 20050258871Abstract: An electronic circuit includes at least one differential pair of transistors, a control transistor switch, a first current source and a second current source. The second current source is connected to a common emitter node of the pair of transistors in order to accelerate the discharge of parasitic capacitances during a switching operation.Type: ApplicationFiled: September 30, 2004Publication date: November 24, 2005Applicant: STMicroelectronics S.A.Inventors: Sebastien Rieubon, Serge Ramet, Philippe Level
-
Patent number: 6822520Abstract: The invention concerns a load pump for phase-locking loop comprising a first current source (14), a second current source (16), several switches (M1, M2, M3, M4) adapted to communicate the first and/or the second current source with the load pump output (OUT). The second current source is driven by control means (18) adapted to store a physical quantity corresponding to the value of the current (11) supplied by the first current source (14), so that the value of the current (12) supplied by the second current source is substantially equal to the value of current (11) supplied by the first current source.Type: GrantFiled: October 15, 2002Date of Patent: November 23, 2004Assignee: STMicroelectronics S.A.Inventors: Serge Ramet, Sébastien Rieubon
-
Patent number: 6680628Abstract: A frequency synthesis method using a phase locked loop including a phase comparator. The method includes switching from a fractional frequency division operating mode to an integer frequency division operating mode after a time or time-delay for stabilizing operation of the loop has elapsed. The method is characterized in that it consists of effecting the operating mode switching by masking or eliminating a portion of the pulses of a reference signal (Sref) and a comparison signal (Scomp) before they are applied to inputs of the phase comparator (3).Type: GrantFiled: May 22, 2002Date of Patent: January 20, 2004Assignee: AlcatelInventors: Arnaud Brunet, Sébastien Rieubon
-
Publication number: 20030062958Abstract: The invention concerns a load pump for phase-locking loop comprising a first current source (14), a second current source (16), several switches (M1, M2, M3, M4) adapted to communicate the first and/or the second current source with the load pump output (OUT). The second current source is driven by control means(18) adapted to store a physical quantity corresponding to the value of the current (11) supplied by the first current source (14), so that the value of the current (12) supplied by the second current source is substantially equal to the value of current (11) supplied by the first current source.Type: ApplicationFiled: October 15, 2002Publication date: April 3, 2003Inventors: Serge Ramet, Sebastien Rieubon
-
Publication number: 20020149430Abstract: The present invention relates to a frequency synthesis system and device using a phase locked loop.Type: ApplicationFiled: May 22, 2002Publication date: October 17, 2002Inventors: Arnaud Brunet, Sebastien Rieubon