Abstract: A method of 3D circuit conception comprising: providing, to a circuit conception tool, circuit design files representing a 3D circuit design including one or more first circuit elements attributed to a first tier of the 3D circuit and one or more second circuit elements attributed to a second tier of the 3D circuit; modifying, by the circuit conception tool, a property of the one or more first and/or second circuit elements to permit any of the second circuit elements to superpose, or be superposed by, any of the first circuit elements; and performing, by the circuit conception tool, placement and routing of the 3D circuit design based on a 2D circuit representation, interconnection nodes of the one or more second circuit elements being defined in one or more interconnection levels of the 2D circuit representation.

Abstract: A tier of a 3D circuit comprising: one or more macro circuits, each macro circuit comprising a plurality of macro cells arranged in an array, the macro cells being separated from each other by spaces; and interconnection vias positioned in the spaces between the macro cells.

Abstract: An integrated circuit including a first chip including a stack of a substrate, of an active layer and of interconnect layers; a second chip including a stack of a substrate, of an active layer and of interconnect layers; an interconnect network for interconnecting the first and second chips. The interconnect layer of the highest metallization level of the first chip includes a power distribution network; the interconnect layer of the highest metallization level of the second chip is without a power distribution network.

Abstract: A method of generating, by a computing device, a 3D circuit layout based on a 2D circuit layout, the method comprising: assigning cells of first and second groups of circuit cells of the 2D circuit layout to first and second levels of the 3D circuit layout, the assignment of each circuit cell of the first and second groups being performed by: selecting, among at least one first row of a first level of the 3D circuit layout and at least one second row of a second level of the 3D circuit layout, the row having the greatest available space; and assigning the circuit cell to the selected row; and transmitting the 3D circuit layout to a manufacturing plant for fabrication.

Abstract: A method of 3D circuit conception comprising: providing, to a circuit conception tool, circuit design files representing a 3D circuit design including one or more first circuit elements attributed to a first tier of the 3D circuit and one or more second circuit elements attributed to a second tier of the 3D circuit; modifying, by the circuit conception tool, a property of the one or more first and/or second circuit elements to permit any of the second circuit elements to superpose, or be superposed by, any of the first circuit elements; and performing, by the circuit conception tool, placement and routing of the 3D circuit design based on a 2D circuit representation, interconnection nodes of the one or more second circuit elements being defined in one or more interconnection levels of the 2D circuit representation.

Abstract: A tier of a 3D circuit comprising: one or more macro circuits, each macro circuit comprising a plurality of macro cells arranged in an array, the macro cells being separated from each other by spaces; and interconnection vias positioned in the spaces between the macro cells.

Abstract: An integrated circuit including a first chip including a stack of a substrate, of an active layer and of interconnect layers; a second chip including a stack of a substrate, of an active layer and of interconnect layers; an interconnect network for interconnecting the first and second chips. The interconnect layer of the highest metallization level of the first chip includes a power distribution network; the interconnect layer of the highest metallization level of the second chip is without a power distribution network.

Abstract: A method of generating, by a computing device, a 3D circuit layout based on a 2D circuit layout, the method comprising: assigning cells of first and second groups of circuit cells of the 2D circuit layout to first and second levels of the 3D circuit layout, the assignment of each circuit cell of the first and second groups being performed by: selecting, among at least one first row of a first level of the 3D circuit layout and at least one second row of a second level of the 3D circuit layout, the row having the greatest available space; and assigning the circuit cell to the selected row; and transmitting the 3D circuit layout to a manufacturing plant for fabrication.

Abstract: The invention concerns a 3D circuit design method implemented by a processing device involving partitioning a 2D circuit representation into two or more tiers, the 2D circuit representation defining circuit elements interconnected by interconnecting wire each weighted based on at least one of: its length; its propagation delay; and its priority level, the 2D circuit representation initially forming a first tier, the partitioning involving: a) selecting a first highest ranking wire, interconnecting at least first and second circuit elements in the first tier; b) moving one of the first and second circuit elements connected by the selected wire to a further tier of the 3D circuit representation and replacing the interconnecting wire with a connecting via between the first and further tiers; and c) repeating a) and b) for one or more further interconnecting wires of the first tier.

Abstract: The invention concerns a 3D circuit design method implemented by a processing device involving partitioning a 2D circuit representation into two or more tiers, the 2D circuit representation defining circuit elements interconnected by interconnecting wire each weighted based on at least one of: its length; its propagation delay; and its priority level, the 2D circuit representation initially forming a first tier, the partitioning involving: a) selecting a first highest ranking wire, interconnecting at least first and second circuit elements in the first tier; b) moving one of the first and second circuit elements connected by the selected wire to a further tier of the 3D circuit representation and replacing the interconnecting wire with a connecting via between the first and further tiers; and c) repeating a) and b) for one or more further interconnecting wires of the first tier.