Patents by Inventor S. Keller

S. Keller has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20080065677
    Abstract: Methods and arrangements to analyze web traffic of a portal are contemplated. Embodiments include transformations, code, state machines or other logic to analyze web traffic of a portal by a portlet receiving a request for web page content from the portal and generating a fragment of a web page. The fragment may include code to collect data from clients on web traffic of the portlet and to transmit the data to a facility for the collection of data on web traffic of the portal and the portlet. Some embodiments may involve a portal requesting web page content from a portlet, and the portal receiving a fragment of a web page from the portlet. The fragment may include code to collect data from clients on web traffic of the portlet and to transmit the data to the data collection facility.
    Type: Application
    Filed: September 12, 2006
    Publication date: March 13, 2008
    Inventors: Steven Howard, Robert S. Keller, Michael S. Nichols, Travis M. Woodruff
  • Patent number: 7260581
    Abstract: In one aspect, the present invention is a web-based system that facilitates rapid and reliable documenting, cataloging, and distributing of proven error proofing techniques. More specifically, and in an exemplary embodiment, a system includes a plurality of clients coupled to a web-based server. Each client includes a plurality of user interface classes and at least one class that provides access to a database. The server includes a plurality of servlets, and at least some of said servlets provide at least one of a database and server access capability to each client. The system further includes a database having a plurality of tables, and at least one of said tables includes at least one error proofing example. The database is accessed by each client via the server.
    Type: Grant
    Filed: January 31, 2000
    Date of Patent: August 21, 2007
    Assignee: General Electric Company
    Inventors: Michael O. Cimini, Jeffrey S. Keller, Gene E. Wiggs, Bethany B. Kniffin, Christopher R. Hammond, Peder Fitch
  • Patent number: 7144417
    Abstract: A chiropractic adjusting instrument comprising a housing; a thrust nose piece and an impact head to contact a body; a preload switch plunger; a dampening spring; a solenoid having a core; a preload spring; a recoil spring; an electronic pulse system operatively connected to a power source to provide alternating current for energizing the solenoid to impart impulse energy from the core to the thrust nose piece which is reproducible and independent of the power source; and a trigger system for triggering the electronic pulse system comprising an switch activated by the preload switch plunger. Preferably, the chiropractic adjusting instrument includes one or more of the following: an intelligent universal AC power converter; optimized force-time waveform; pulse mode operation; and a suite of electromechanical components designed to promote reproducible dynamic force impulses and safe operation.
    Type: Grant
    Filed: August 26, 2005
    Date of Patent: December 5, 2006
    Inventors: Christopher J. Colloca, Tony S. Keller
  • Patent number: 7115274
    Abstract: The present invention provides a method of using autologous fibroblasts to promote wound or fistula healing in an animal.
    Type: Grant
    Filed: January 21, 2005
    Date of Patent: October 3, 2006
    Assignee: Isolagen Technologies, Inc.
    Inventors: Gregory S. Keller, Elena Revazova
  • Patent number: 6974474
    Abstract: A multiple-sided medical device comprises a closed frame of a single piece of wire or other resilient material and having a series of bends and interconnecting sides. The device has both a flat configuration and a second, folded configuration that comprises a self-expanding stent. The stent is pushed from a delivery catheter into the lumen of a duct or vessel. One or more barbs are attached to the frame of the device for anchoring or to connect additional frames. A covering of fabric or other flexible material such as DACRON, PTFE, or collagen, is sutured or attached to the frame to form an occlusion device, a stent graft, or an artificial valve such as for correcting incompetent veins in the lower legs and feet. A partial, triangular-shaped covering over the lumen of the device allows the valve to open with normal blood flow and close to retrograde flow.
    Type: Grant
    Filed: November 14, 2002
    Date of Patent: December 13, 2005
    Assignee: Cook Incorporated
    Inventors: Dusan Pavcnik, Frederick S. Keller, Josef Rosch, Thomas A. Osborne
  • Patent number: 6973361
    Abstract: The present invention relates to a method for optimizing the performance of a process, especially where the process is performed at several different locations. In one embodiment, one or more experts produce a decision tree for use in determining a recommended sequence of steps for the process. A computer network, such as the World Wide Web, is used to convey a request to a computer that has access to the decision tree for a recommended sequence of steps. The request includes any information that is needed by the decision tree to determine the recommended sequence of steps. In response to the request, the computer uses the information in the request and the decision tree to produce the recommended sequence of steps. The recommended sequence of steps is then directed over the network to the user.
    Type: Grant
    Filed: March 21, 2000
    Date of Patent: December 6, 2005
    Assignee: General Electric Company
    Inventors: Christopher R. Hammond, Jeffrey S. Keller, David A. Beach
  • Publication number: 20050210425
    Abstract: A method for controlling analysis by an analysis tool of multiple instantiations of a circuit in a hierarchical circuit design is described. The method comprises providing a user-selected analysis option to the analysis tool; analyzing a first instantiation of the circuit as specified by the analysis option; and responsive to the first instantiation of the circuit passing the analysis, terminating analysis of the circuit.
    Type: Application
    Filed: March 18, 2004
    Publication date: September 22, 2005
    Inventors: S. Keller, Gregory Rogers, George Robbert
  • Publication number: 20050210429
    Abstract: A method of using a software tool to analyze a VLSI circuit is described. In one embodiment, the method comprises, prior to initiating analysis of the circuit, performing a complexity check on the circuit; responsive to the circuit failing the complexity check, aborting analysis of the circuit; and responsive to the circuit passing the complexity check, initiating analysis of the circuit and continuing analysis of the circuit until expiration of a predetermined time period following the initiating.
    Type: Application
    Filed: March 18, 2004
    Publication date: September 22, 2005
    Inventors: S. Keller, Gregory Rogers, George Robbert
  • Publication number: 20050210426
    Abstract: A method for use by a circuit analysis tool for selectively applying configuration information from multiple sources to configuration data elements (“CDEs”) stored in a database is described. The method comprises comparing a data source indicator (“DSI”) of a configuration command with a DSI of a corresponding CDE; if the DSI of the configuration command takes precedence over the DSI of the corresponding CDE, applying the configuration command thereto; and if the DSI of the configuration command does not take precedence over the DSI of the corresponding CDE, disregarding the configuration command.
    Type: Application
    Filed: March 18, 2004
    Publication date: September 22, 2005
    Inventors: S. Keller, Gregory Rogers, George Robbert
  • Publication number: 20050210430
    Abstract: A method for optimizing relationships between logic commands defining a circuit design is described. The method comprises, for each logic command determining whether the logic command is a primitive logic command; and, responsive to the logic command not being a primitive logic command, decomposing the logic command into its most primitive form.
    Type: Application
    Filed: March 18, 2004
    Publication date: September 22, 2005
    Inventors: S. Keller, Gregory Rogers, George Robbert
  • Publication number: 20050210427
    Abstract: A method for optimizing relationships between logic commands defining a circuit design input to an analysis tool is described. The method comprises, responsive to a determination that a value of logic level of a signal can be inferred and responsive to an attempt by the analysis tool to set the logic level of the signal to a calculated value, determining whether the calculated value is equal to the inferred value; and if the calculated value is equal to the inferred value, setting the logic level of the signal to the inferred value.
    Type: Application
    Filed: March 18, 2004
    Publication date: September 22, 2005
    Inventors: S. Keller, Gregory Rogers, George Robbert
  • Publication number: 20050210428
    Abstract: One embodiment is a method for enabling a first circuit analysis tool to flatten a hierarchical design for processing by a second circuit analysis tool. The method comprises reading a logical representation of the hierarchical design; and, for each block of the hierarchical design, loading RC information for the block from an RC model of the hierarchical design and writing a flat representation of each instantiation of the block to the second circuit analysis tool.
    Type: Application
    Filed: March 18, 2004
    Publication date: September 22, 2005
    Inventors: S. Keller, Gregory Rogers, George Robbert
  • Publication number: 20050050503
    Abstract: A method and system for establishing consistency, with respect to a data model, between sub-modules within an E-CAD tool. A consistency database, including at least one consistency indicator for each block of interest in the data model, is initially created. One or more of the sub-modules is then executed to perform an analysis of a current version of the data model. At least one data field value, corresponding to the consistency indicator, is compared for each block of interest, in source files in the current version of the data model being analyzed, against a corresponding consistency indicator in the consistency database. A warning is issued, indicating a possible discrepancy between data in the current version of the data model and corresponding data in a previous version of the data model, if a difference is detected between at least one data field value in the current version of the data model being analyzed and the corresponding consistency indicator.
    Type: Application
    Filed: August 25, 2003
    Publication date: March 3, 2005
    Inventors: S. Keller, Gregory Rogers, George Robbert
  • Publication number: 20050050506
    Abstract: A method and system for determining connectivity of a hierarchical circuit design. Hierarchical interface connections in the circuit design are evaluated by determining, for each block instance in each of the hierarchical blocks in the design, whether each port instance, on each block instance, is connected a net in a parent block; and whether each port, in each of the hierarchical blocks, is connected to a net within the block. A warning message is generated upon detection of at least one disconnected net within the hierarchical blocks.
    Type: Application
    Filed: August 25, 2003
    Publication date: March 3, 2005
    Inventors: S. Keller, Gregory Rogers, George Robbert
  • Publication number: 20050050484
    Abstract: Methods, systems, software products analyze a circuit design with reduced memory utilization. Access to at least one block of the circuit design is detected. If the one block is not loaded within a circuit model of computer memory, a determination is made whether loading the one block into the circuit model would exceed a predefined maximum utilization of the computer memory. If loading the one block into the circuit model would exceed the predefined maximum utilization, one or more blocks from the circuit model are unloaded and the one block is loaded into the circuit model. If loading the one block into the circuit model would not exceed the predefined maximum utilization, the one block is loaded into the circuit model.
    Type: Application
    Filed: August 25, 2003
    Publication date: March 3, 2005
    Inventors: S. Keller, Gregory Rogers, George Robbert
  • Publication number: 20050050481
    Abstract: Systems, methods and software products determine activity factors of a circuit design. An activity factor is assigned to one or more node types. One or more signal nets from a netlist of the circuit design are read. The signal nets are processed to associate one of the node types with each of the signal nets. An activity factor is determined for each of the signal nets based upon node type.
    Type: Application
    Filed: August 25, 2003
    Publication date: March 3, 2005
    Inventors: S. Keller, Gregory Rogers, George Robbert
  • Publication number: 20050050485
    Abstract: Systems, methods, software products identify a data source used in analysis of a circuit design. Data source information, including identification of the data source used to generate data for an entity in a design portion of interest in the circuit design, is retrieved. The data source information is formatted as a bit vector associated with the entity, wherein each of a plurality of bits in the bit vector comprises indicia applicable to the entity. The bit vector is processed to generate formatted output.
    Type: Application
    Filed: August 25, 2003
    Publication date: March 3, 2005
    Inventors: S. Keller, Gregory Rogers, George Robbert
  • Publication number: 20050050493
    Abstract: A system and method for determining unmatched design elements in a circuit. The system determines instances of a first type and a second type of the design elements that are connected to a specific node in the circuit, and stores the gate signal name for each determined said occurrence of the first type of design element in a first list. The gate signal name for each determined said occurrence of the second type of design element is than stored in a second list. A value of a design element characteristic and indicia thereof for each determined said occurrence of the first and the second types of the design elements is than stored.
    Type: Application
    Filed: August 25, 2003
    Publication date: March 3, 2005
    Inventors: S. Keller, Gregory Rogers, George Robbert
  • Publication number: 20050050486
    Abstract: Systems, methods, software products utilize fast analysis information during detailed analysis of a circuit design. One or more design blocks of the circuit design are electronically analyzed to determine fast analysis results based upon assumptions of ported signal nets of each one of the design blocks. Next, it is determined whether hierarchical signal net connectivity of block instances of the design blocks and the assumptions match. If the hierarchical signal net connectivity matches the assumptions, the fast analysis results are utilized to generate detailed analysis results. If the hierarchical signal net connectivity does not match the assumptions, the one or more blocks in the hierarchical signal net connection are electronically analyzed to generate detailed analysis results.
    Type: Application
    Filed: August 25, 2003
    Publication date: March 3, 2005
    Inventors: S. Keller, Gregory Rogers, George Robbert
  • Publication number: 20050050491
    Abstract: A method and system for determining wire capacitance for a VLSI circuit design, comprising determining all hierarchical blocks of a portion of the design; storing, for a plurality of the blocks, indicia of the most accurate one of a plurality of wire capacitance data sources; generating a wire capacitance database with an entry for each net in at least a plurality of the blocks, using information stored in at least one of the wire capacitance data sources; generating a hierarchical connectivity model for the design; and using the hierarchical connectivity model and said wire capacitance database to determine a cumulative wire capacitance value for each HLSN in each of the blocks in a portion of the design to be analyzed.
    Type: Application
    Filed: August 25, 2003
    Publication date: March 3, 2005
    Inventors: S. Keller, Gregory Rogers, George Robbert