Patents by Inventor S M Istiaque Hossain

S M Istiaque Hossain has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220028881
    Abstract: An electronic device comprising lower and upper decks adjacent to a source. The lower and upper decks comprise tiers of alternating conductive materials and dielectric materials. Memory pillars in the lower and upper decks are configured to be operably coupled to the source. The memory pillars comprise contact plugs in the upper deck, cell films in the lower and upper decks, and fill materials in the lower and upper decks. The cell films in the upper deck are adjacent to the contact plugs and the fill materials in the upper deck are adjacent to the contact plugs. Dummy pillars are in a central region of the lower deck and the upper deck. The dummy pillars comprise an oxide material in the upper deck, the oxide material contacting the contact plugs and the fill materials. Additional electronic devices and related systems and methods are also disclosed.
    Type: Application
    Filed: July 23, 2020
    Publication date: January 27, 2022
    Inventors: S M Istiaque Hossain, Tom J. John, Darwin A. Clampitt, Anilkumar Chandolu, Prakash Rau Mokhna Rau, Christopher J. Larsen, Kye Hyun Baek
  • Publication number: 20210327885
    Abstract: An electronic device comprising a lower deck and an upper deck adjacent to a source. Each of the lower deck and the upper deck comprise tiers of alternating conductive materials and dielectric materials. Each of the lower deck and the upper deck also comprise an array region and one or more non-array regions. Memory pillars are in the lower deck and the upper deck of the array region and the memory pillars are configured to be operably coupled to the source. Dummy pillars are in the upper deck of the one or more non-array regions and the dummy pillars are configured to be electrically isolated from the source. Another conductive material is in the upper deck and the lower deck of the one or more non-array regions. Additional electronic devices and related systems and methods of forming an electronic device are also disclosed.
    Type: Application
    Filed: April 17, 2020
    Publication date: October 21, 2021
    Inventors: S M Istiaque Hossain, Christopher J. Larsen, Anilkumar Chandolu, Wesley O. McKinsey, Tom J. John, Arun Kumar Dhayalan, Prakash Rau Mokhna Rau
  • Publication number: 20210272845
    Abstract: A method of forming a microelectronic device comprises forming a stack structure comprising vertically alternating insulating structures and additional insulating structures arranged in tiers. Each of the tiers individually comprises one of the insulating structures and one of the additional insulating structures. A first trench is formed to partially vertically extend through the stack structure. The first trench comprises a first portion having a first width, and a second portion at a horizontal boundary of the first portion and having a second width greater than the first width. A dielectric structure is formed within the first trench. The dielectric structure comprises a substantially void-free section proximate the horizontal boundary of the first portion of the trench. Microelectronic devices and electronic systems are also described.
    Type: Application
    Filed: May 14, 2021
    Publication date: September 2, 2021
    Inventors: Anilkumar Chandolu, Christopher R. Ritchie, Darwin A. Clampitt, S M Istiaque Hossain
  • Patent number: 11101280
    Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a stack comprising vertically-alternating first tiers and second tiers comprising memory-block regions having channel-material strings therein. Conductor-material contacts are directly against the channel material of individual of the channel-material strings. First insulator material is formed directly above the conductor-material contacts. The first insulator material comprises at least one of (a) and (b), where (a): silicon, nitrogen, and one or more of carbon, oxygen, boron, and phosphorus, and (b): silicon carbide. Second insulator material is formed directly above the first insulator material and the conductor-material contacts. The second insulator material is devoid of each of the (a) and (b). Third insulator material is formed directly above the second insulator material, the first insulator material, and the conductor-material contacts. The third insulator material comprises at least one of the (a) and (b).
    Type: Grant
    Filed: December 27, 2019
    Date of Patent: August 24, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Anilkumar Chandolu, S.M. Istiaque Hossain, Darwin A. Clampitt, Arun Kumar Dhayalan, Kevin R. Gast, Christopher Larsen, Prakash Rau Mokhna Rau, Shashank Saraf
  • Publication number: 20210202515
    Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a stack comprising vertically-alternating first tiers and second tiers comprising memory-block regions having channel-material strings therein. Conductor-material contacts are directly against the channel material of individual of the channel-material strings. First insulator material is formed directly above the conductor-material contacts. The first insulator material comprises at least one of (a) and (b), where (a): silicon, nitrogen, and one or more of carbon, oxygen, boron, and phosphorus, and (b): silicon carbide. Second insulator material is formed directly above the first insulator material and the conductor-material contacts. The second insulator material is devoid of each of the (a) and (b). Third insulator material is formed directly above the second insulator material, the first insulator material, and the conductor-material contacts. The third insulator material comprises at least one of the (a) and (b).
    Type: Application
    Filed: December 27, 2019
    Publication date: July 1, 2021
    Applicant: Micron Technology, Inc.
    Inventors: Anilkumar Chandolu, S.M. Istiaque Hossain, Darwin A. Clampitt, Arun Kumar Dhayalan, Kevin R. Gast, Christopher Larsen, Prakash Rau Mokhna Rau, Shashank Saraf
  • Patent number: 11043412
    Abstract: A method of forming a microelectronic device comprises forming a stack structure comprising vertically alternating insulating structures and additional insulating structures arranged in tiers. Each of the tiers individually comprises one of the insulating structures and one of the additional insulating structures. A first trench is formed to partially vertically extend through the stack structure. The first trench comprises a first portion having a first width, and a second portion at a horizontal boundary of the first portion and having a second width greater than the first width. A dielectric structure is formed within the first trench. The dielectric structure comprises a substantially void-free section proximate the horizontal boundary of the first portion of the trench. Microelectronic devices and electronic systems are also described.
    Type: Grant
    Filed: August 5, 2019
    Date of Patent: June 22, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Anilkumar Chandolu, Christopher R. Ritchie, Darwin A. Clampitt, S M Istiaque Hossain
  • Publication number: 20210043504
    Abstract: A method of forming a microelectronic device comprises forming a stack structure comprising vertically alternating insulating structures and additional insulating structures arranged in tiers. Each of the tiers individually comprises one of the insulating structures and one of the additional insulating structures. A first trench is formed to partially vertically extend through the stack structure. The first trench comprises a first portion having a first width, and a second portion at a horizontal boundary of the first portion and having a second width greater than the first width. A dielectric structure is formed within the first trench. The dielectric structure comprises a substantially void-free section proximate the horizontal boundary of the first portion of the trench. Microelectronic devices and electronic systems are also described.
    Type: Application
    Filed: August 5, 2019
    Publication date: February 11, 2021
    Inventors: Anilkumar Chandolu, Christopher R. Ritchie, Darwin A. Clampitt, S M Istiaque Hossain