Abstract: A power switch circuit and method is provided for having the capability of (1) a power switch circuit having a POR in which the switch is enabled at a predetermined voltage such that the switch is unable to be activated when a minimum lower input voltage is not achieved, to avoid potential conflicts in synchronization and resets with other integrated circuits or chips of an affected system; (2) a POR designed with a delay circuit providing for coordinated stabilization of the power switch before each ON-OFF transition period; (3) using a controlled peaking current in the POR circuit to provide precise RC delay to avoid instability during transition; and (4) a POR providing an externally controlled voltage to power-up other components in the system when energizing of the first component occurs satisfactorily.

Abstract: The present invention relates generally to semiconductor wafer fabrication and more particularly but not exclusively to predictive, pre-fabrication methodologies for determining inefficiencies in an integrated circuit (IC) design. The present invention, in one or more implementations, provides an effective pre-production methodology for predicting the efficiency and behavior of a designed ESD protective circuit and testing the ESD protective circuit with a simulated IC. The method of the present invention yields predictive results that have been comparatively tested.

Abstract: An optimized output voltage circuit and technique obtainable without trimming is set forth. A voltage reference circuit and method devoid of trim resistors comprising a high gain amplifier, a plurality of bandgap resistors, and at least a plurality of bipolar devices interconnected across circuitry in a predetermined configuration having emitter areas greater than traditional emitter areas of traditional bipolar devices is set forth.

Abstract: A power switch circuit and method is provided for having the capability of (1) a power switch circuit having a POR in which the switch is enabled at a predetermined voltage such that the switch is unable to be activated when a minimum lower input voltage is not achieved, to avoid potential conflicts in synchronization and resets with other integrated circuits or chips of an affected system; (2) a POR designed with a delay circuit providing for coordinated stabilization of the power switch before each ON-OFF transition period,; (3) using a controlled peaking current in the POR circuit to provide precise RC delay to avoid instability during transition; and (4) a POR providing an externally controlled voltage to power-up other components in the system when energizing of the first component occurs satisfactorily.

Abstract: An optimized output voltage circuit and technique obtainable without trimming is set forth. A voltage reference circuit and method devoid of trim resistors comprising a high gain amplifier, a plurality of bandgap resistors, and at least a plurality of bipolar devices interconnected across circuitry in a predetermined configuration having emitter areas greater than traditional emitter areas of traditional bipolar devices is set forth.

Abstract: A voltage regulator output stage can include a power device whose body to source junction is forward biased using a MOSFET trigger. The forward biasing can advantageously reduce the threshold voltage of the power device, thereby effectively increasing its gate drive as well as its output current capability. Controlling the forward biasing using the MOSFET trigger provides minimal leakage, thereby ensuring that the output stage is commercially viable as well as performance enhanced.

Abstract: A thermal shutdown system that can accurately detect a chip overheat condition or a local overheat condition is described. This system can include a first shutdown circuit triggered by the chip overheat condition and a second shutdown circuit triggered by the local overheat condition. The second shutdown circuit can be located near the heat-generating component on the IC. The first shutdown circuit can be located in another area of the IC. A common temperature independent signal, which indicates whether a local overheat condition is anticipated, can enable one shutdown circuit and disable the other shutdown circuit. An enabled shutdown circuit can respond to a temperature sensitive signal to indicate a fault condition, i.e. Ea chip/local overheat condition.

Abstract: A voltage regulator output stage can include a power device whose body to source junction is forward biased using a MOSFET trigger. The forward biasing can advantageously reduce the threshold voltage of the power device, thereby effectively increasing its gate drive as well as its output current capability. Controlling the forward biasing using the MOSFET trigger provides minimal leakage, thereby ensuring that the output stage is commercially viable as well as performance enhanced.

Abstract: A thermal shutdown system that can accurately detect a chip overheat condition or a local overheat condition is described. This system can include a first shutdown circuit triggered by the chip overheat condition and a second shutdown circuit triggered by the local overheat condition. The second shutdown circuit can be located near the heat-generating component on the IC. The first shutdown circuit can be located in another area of the IC. A common temperature independent signal, which indicates whether a local overheat condition is anticipated, can enable one shutdown circuit and disable the other shutdown circuit. An enabled shutdown circuit can respond to a temperature sensitive signal to indicate a fault condition, i.e. a chip/local overheat condition.