Abstract: The present invention relates to a parallel multithread processor (1) with split contexts, with M parallel-connected standard processor root units (2) being provided for instruction execution of program instructions for different threads (T), and with N context memories (3) being provided, which each temporarily store a current state of a thread (T), and with a thread monitoring unit (4) being provided, by means of which each standard processor root unit (2) can be connected to each context memory (3). The invention accordingly provides a processor architecture in which a number N of different context memories (3) and corresponding threads (T) are effectively fully networked with a number M of standard processor root units (2). This means that use is made not only of paralleling of the standard processor root units (2), but also of the threads (T) and of the context memories (3).

Abstract: A radio receiver with a low intermediate frequency has a first mixer stage that can be fed with a modulated input signal and at whose output a complex intermediate frequency signal can be derived. Connected downstream of the first mixer stage is a limiting amplifier at whose output the intermediate frequency signal is present in a discrete-value and continuous-time fashion. A sampling device, for sampling the intermediate frequency signal, and a digital demodulator unit are connected to the output of this limiter. The demodulated input signal can be derived at the output of this digital demodulator unit. The present radio receiver requires a low chip area in conjunction with low power consumption, but offers a high sensitivity and accuracy based on the digitally implemented demodulation.

Abstract: The invention relates to a heterogeneous parallel multithread processor (1) with shared contexts which has a plurality (M) of parallel-connected standard processor root unit types (2p; p? [1, . . . , M]), where each respective standard processor root unit type (2p) has at least one or more (K) parallel-connected standard processor root units (2pq; q? [1, . . . , K]) for instruction execution of program instructions from various threads (T), each standard processor root unit type (2p) having N local context memories (32pt) which each buffer-store part of a current processor state for a thread. The multithread processor (1) also has a plurality (N) of global context memories (3t; t? [1, . . . , N]) which each buffer-store part of a current processor state for a thread, and a thread control unit (4) which can connect any standard processor root unit (2pq) to any global context memory (3t).

Abstract: Channel selection of a received signal is first of all carried out, in the process, by way of an analog channel selection filter. The signal is then converted to a digital discrete-time and discrete-value signal. Finally, the continuous-time and continuous-value signal profile is determined on the basis of a mathematical reconstruction using the zero crossings {ti} and the phase values {?(ti)=ki·?/2, ki?N0}, with a mathematical reconstruction algorithm using a function system {?(t?k)}.

Abstract: The present invention relates to a parallel multithread processor (1) with split contexts, with M parallel-connected standard processor root units (2) being provided for instruction execution of program instructions for different threads (T), and with N context memories (3) being provided, which each temporarily store a current state of a thread (T), and with a thread monitoring unit (4) being provided, by means of which each standard processor root unit (2) can be connected to each context memory (3). The invention accordingly provides a processor architecture in which a number N of different context memories (3) and corresponding threads (T) are effectively fully networked with a number M of standard processor root units (2). This means that use is made not only of paralleling of the standard processor root units (2), but also of the threads (T) and of the context memories (3).

Abstract: The invention relates to a heterogeneous parallel multithread processor (1) with shared contexts which has a plurality (M) of parallel-connected standard processor root unit types (2p; p?[1, . . . , M]), where each respective standard processor root unit type (2p) has at least one or more (K) parallel-connected standard processor root units (2pq; q?[1, . . . , K]) for instruction execution of program instructions from various threads (T), each standard processor root unit type (2p) having N local context memories (32pt) which each buffer-store part of a current processor state for a thread. The multithread processor (1) also has a plurality (N) of global context memories (3t; t?[1, . . . , N]) which each buffer-store part of a current processor state for a thread, and a thread control unit (4) which can connect any standard processor root unit (2pq) to any global context memory (3t).

Abstract: A circuit configuration for a multistandard communications terminal has, for the reception of radio signals, a radio frequency component with a receive conversion stage and a signal-processing circuit connected downstream of the radio frequency component. The signal-processing circuit has an A/D converter and a digital filter. The pass-band of the digital filter is variable. In operation, the pass-band is set according to a selected system standard of the received radio signals.

Abstract: A filter for filtering n data trains by time division multiplexing includes data channels for receiving data train values, registers subdivided into n groups for buffer storage of the data train values or derived values, and adders each having inputs. Each of the n groups is connected to one of the data channels. The adders and the registers alternatively connect to form a chain. The first input of respective adders connected upstream of a respective register of an ith group (0≦i≦n−1) has a connection to respective data channels assigned to the ith group, and the second input is connected to a respective register of a group having a number (i−1)mod n without an intervening register of another group. The filter is used to parallelly decimate data trains by a common factor. A filter configuration includes the filter and two multipliers. A method is also provided.

Abstract: The operation of any desired number of initially unidentified slave stations in a communications system is possible. An identification procedure with a subsequent address assignment is carried out by a master station M, in that all the slave stations simultaneously output bit by bit, via open-drain output circuits OC, individual identification codes ID which are stored in them.

Abstract: The circuit simultaneously filters and decimates a video signal formed with samples for luminance and chrominance. A subcircuit provides the samples in distinct sequences with alternate luminance and chrominance values. A filter stage is provided which contains a first adder which is supplied with one of the sequences via a first register. The other terminal of the adder is supplied with the other sequence. A second register can be directly connected to the adder if luminance samples are processed, and via a third register if chrominance samples are processed. The output signal of the second register is combined with the samples of one of the sequences by means of an adder at the output end. In the case of a higher degree of the filter, a number of filter stages are cascaded (connected in series). Where a higher degree of decimation is required, feedback is provided in each filter stage.

Abstract: A bus arbitration method for a multimaster system comprising a plurality of masters sharing a global data bus and a plurality of bus arbiters sharing a global identification bus. Each active bus arbiter applies to the identification bus a bus request signal containing a k-bit-wide identification word representative of the priority of the master associated with the bus arbiter. In each prioritization step of the bus grant cycle, a logic level is produced on the identification bus by logically combining bits of equal significance. This logic level is then compared with the corresponding bits of the applied identification words.

Abstract: For improved offset compensation, a Hall sensor is provided with a device for orthogonally switching the Hall detector supply current and the Hall-voltage taps. A summing device determines an offset-compensated Hall-voltage value from first and second predetermined Hall-voltage values. The Hall-voltage values are formed by means of a Hall detector containing at least first and second Hall cells for offset-voltage precompensation. The first and second Hall cells are identical and are orthogonally switchable. The geometrical orientation of the first and second Hall cells includes an angle other than 0.degree. and 180.degree..

Abstract: A digital television-signal-processing circuit for a composite color signal is sampled with a first clock signal. The digitized composite color signal is reconverted with a line-locked second clock signal. The two clock signals have the same frequency. A second phase-locked loop for controlling the phase of the horizontal pulse includes a locked oscillator and is loosely coupled to a first phase-locked loop which generates a horizontal reference clock. The decoupling of the data, which is referred to the two clock signals, takes place in a dual-port read/write memory which is written into synchronously with the first clock signal and read from synchronously with the second clock signal.

Abstract: In a median filter, signals received at the input are fed to a cascade of delay elements whose number is equal to the degree N of the median filter. The signals at the outputs of the delay elements which preceded the signal received at the input are fed to N subtracters which form the differences between the signal at the input and the N preceding signals. The signs of the differences are stored in shift registers, and upon receipt of a new signal at the input, they are shifted by one place. From the signs of the differences, the selection unit determines the median as the signal for which N/2 differences have negative signs and N/2 differences have positive signs.

Abstract: A central processor for digital signal processing operates at a high clock rate. In the central processor, data is transferred and processed largely in parallel and simultaneously. A buffer is inserted in the data link between a data memory and an ALU by means of at least three data buses so that within one clock period, all necessary data transfers for a two-address operation of the ALU are performed by using the buffer. In particular, a unidirectional data bus and a bidirectional data bus transfer data from the buffer to the ALU, and the bidirectional data bus transfers the result of an ALU operation back to the buffer. Simultaneously with the transfers between the buffer and the ALU, a data transfer is performed between the data memory and the buffer. The data transfers and the data processing are controlled by a control unit in which a fixed program is stored segment by segment. The use of pipelining in the control unit permits a high processing speed.

Abstract: A digital color-signal-processing circuit generates a phase-angle signal and a magnitude signal as outputs in response to an R-Y color-difference signal and a B-Y color-difference signal. The circuit includes a resolver which convertes cartesian coordinate representations of the color-difference signals into polar coordinate representations of the phase-angle signal and the magnitude signal. The phase-angle signal carries the hue information, which is processed in a hue stage. The magnitude signal carries the saturation information, which is processed in a saturation stage. The processed phase-angle signal and the processed magnitude signal are reconverted to cartesian coordinate representations of the R-Y and B-Y color-difference signals in a reconverting resolver.

Abstract: A deflection processor generates deflection signals such that the video information of the received signal is visible on the picture tube screen during all movements of the cathode ray beam. The video signal, after being digitized by means of a clock signal, is written into a random-access memory and is read therefrom in such a way that the individual pixels occupy the correct positions on the screen. This is done under control of a memory controller. The digital signals of the memory are applied to a tube-error-compensating stage and to the picture tube via digital-to-analog converters. This arrangement eliminates the rigid dependence on sawtooth deflection signals and permits the waveforms of the deflection signals to be freely selected according to requirements.

Abstract: The signal path of a nonrecursive digital filter contains a series combination of like delay elements each providing a delay equal to the period of a clock signal or to a multiple thereof, each of the delay elements having a subtracter and a read-only memory associated therewith. The minuend inputs of each of the subtracters associated with the first half of delay elements is connected to the input of the associated delay element, and that of each of the substracters associated with the second half of delay elements to the output of the associated delay element, while the subtrahend inputs of all subtracters are connected to the center tap of the series combination of delay elements and to the first input of an adder. The output of each of the subtracters is coupled to the address input of the associated read-only memory, which has its output connected to one of the inputs of a multiple-input adder. The output of the latter is fed to the second input of the adder.

Abstract: This circuit simultaneously provides the sine- and cosine-function values for one and the same digital argument from any of the quadrants of the sine and cosine functions. Stored in the two halves of a read-only memory are the unsigned function values of the first half-quadrant of the cosine function in the direction of increasing arguments and of the second half-quadrant in the direction of decreasing arguments, respectively. The number of bits of the argument is greater than the number of bits of the function values, including the sign bit, by two. By skillful inversion of the addresses and the read-out function values using multiple-inverter blocks in conjunction with multiple-switch units sine- and cosine-function values can be generated for all four quadrants both in the one's and in the two's complement code. If the argument is formed by an accumulator fed with the frequency determining digital word, the digital circuit is a digital sine-/cosine-wave oscillator.

Abstract: Instead of fine-controlling the horizontal deflection signal in a digital television receiver by means of two phase-locked loops and gate-delay stages as is done in prior art arrangements, in the horizontal-deflection circuit according to the invention, a first digital word delivered by a first phase-locked loop and representative of the horizontal frequency is added in an adder to a suitably amplified third digital word delivered by a phase comparator of a second phase-locked loop. The output of the adder is fed to the control input of a digital sine-wave generator which drives a frequency divider. The latter delivers the horizontal deflection signal, which drives the horizontal output stage. The phase comparator is fed with the horizontal flyback signal, which is derived from the horizontal deflection signal, and a second digital word generated by the first phase-locked loop and representative of the desired phase position of the flyback signal.