Abstract: A vertical Triple Heterojunction Bipolar Transistor (THBT) and method of fabrication therefor. The THBT collector has a substrate layer of N.sup.+ silicon, an N.sup.- silicon layer grown on the substrate and a Si/SiGe superlattice grown on the N.sup.- silicon layer. The THBT base is layer of P.sup.+ SiGe grown on the superlattice. The THBT Emitter is a second Si/SiGe Superlattice grown on the base layer. An N.sup.- silicon layer is grown on the emitter superlattice. A layer of N.sup.+ GaP grown on that N.sup.- Si layer. The base is formed, first, by etching a rectangular groove through the emitter, ion implanting dopant into the base layer to form an extrinsic base, etching a V shaped groove into the extrinsic base and, then, filling the grooved base with doped polysilicon.

Abstract: A vertical Metal Oxide Semiconductor Heterojunction Field Effect Transistor (MOSHFET) and method of fabrication therefor. The MOSHFET is in a layered wafer made by successively growing an N.sup.+ silicon layer, and a N.sup.- silicon layer, a P.sup.- Si.sub.1-x Gex layer, a P.sup.- Silicon layer and then, an N.sup.- silicon layer, one on top of the other. Trenches are etched through the top 3 layers to form islands that are the MOSHFETs heterojunction channel. A gate deposited or grown in a trench extends vertically from the drain at the bottom of the trench to the source in the layer near the top of the trench.

Abstract: A vertical Triple Heterojunction Bipolar Transistor (THBT) and method of fabrication therefor. The THBT collector has a substrate layer of N.sup.+ silicon, an N.sup.- silicon layer grown on the substrate and a Si/SiGe superlattice grown on the N.sup.- silicon layer. The THBT base is layer of P.sup.+ SiGe grown on the superlattice. The THBT Emitter is a second Si/SiGe Superlattice grown on the base layer. An N.sup.- silicon layer is grown on the emitter superlattice. A layer of N.sup.+ GaP grown on that N.sup.- Si layer. The base is formed, first, by etching a rectangular groove through the emitter, ion implanting dopant into the base layer to form an extrinsic base, etching a V shaped groove into the extrinsic base and, then, filling the grooved base with doped polysilicon.

Abstract: A superheterojunction Field Effect Transistor (FET) with a multi-region channel on a Silicon (Si) substrate. The FET is a Metal Semiconductor FET (MESFET) or, alternatively, a Junction FET (JFET). The multi-region channel has: A first region of Si extending from the FET's source to a point under the FET's gate, beyond the gate's midpoint; a second region extending from the first region to the FET's drain, comprised of a superlattice of alternating Si and SiGe layers; and, a third region of Si extending under the first two regions from the source to the drain. The first region has a laterally graded dopant that creates an accelerating electric field. The superlattice structure increases electron mobility and transit velocity.

Abstract: A Double Heterojunction Bipolar Transistor (DHBT) and the method of fabrication therefor. First a layered wafer is prepared on a semi-insulating GaAs substrate. The bottom wafer layer is n.sup.+ GaAs, followed by n.sub.- AlGaAs, a thin layer of n AlGaAs (which form the DHBT's collector) and a base layer of p.sup.+ GaAS. A layered plug fills a trench etched in the base layer. The bottom two plug layers are AlGaAs and the top plug layer is GaAs. Next, an emitter is ion-implanted into the plug core and an extrinsic base region is ion-implanted. Finally, base, emitter and collector contacts are formed.

Abstract: A Metal Insulator Semiconductor (MIS) heterojunction transistor. The MIS transistor is in a layered wafer having a n.sup.+ Si substrate, n Si collector layer, and a p Si/SiGe base. The base Si/SiGe interface may be vertical or horizontal. A thin oxide layer separates the base from the emitter, which is of a low work function metal such as Al, Mg, Mn, or Ti.

Abstract: Method of fabricating a vertical Metal Oxide Semiconductor Heterojunction Field Effect Transistor (MOSHFET) which is in a layered wafer made by successively growing an N.sup.+ silicon layer, and a N.sup.- silicon layer, a P.sup.- Si.sub.1-x Gex layer, a P.sup.- Silicon layer and then, an N.sup.- silicon layer, one on top of the other. Trenches are etched through the top 3 layers to form islands that are the MOSHFETs heterojunction channel. A gate deposited or grown in a trench extends vertically from the drain at the bottom of the trench to the source in the layer near the top of the trench.

Abstract: A Double Heterojunction Bipolar Transistor (DHBT) and the method of fabrication therefor. First a layered wafer is prepared on a semi-insulating GaAs substrate. The bottom wafer layer is n.sup.+ GaAs, followed by n.sub.- AlGaAs, a thin layer of n AlGaAs (which form the DHBT's collector) and a base layer of p.sup.+ GaAS. A layered plug fills a trench etched in the base layer. The bottom two plug layers are AlGaAs and the top plug layer is GaAs. Next, an emitter is ion-implanted into the plug core and an extrinsic base region is ion-implanted. Finally, base, emitter and collector contacts are formed.

Abstract: A superheterojunction Field Effect Transistor (FET) with a multi-region channel on a Silicon (Si) substrate. The FET is a Metal Semiconductor FET (MESFET) or, alternatively, a Junction FET (JFET). The multi-region channel has: A first region of Si extending from the FET's source to a point under the FET's gate, beyond the gate's midpoint; a second region extending from the first region to the FET's drain, comprised of a superlattice of alternating Si and SiGe layers; and, a third region of Si extending under the first two regions from the source to the drain. The first region has a laterally graded dopant that creates an accelerating electric field. The superlattice structure increases electron mobility and transit velocity.