Patents by Inventor S.O.I Tec Silicon on Insulator Technologies

S.O.I Tec Silicon on Insulator Technologies has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20130146805
    Abstract: The present disclosure provides a chemical etchant which is capable of removing Ge and Ge-rich SiGe alloys in a controlled manner. The chemical etchant of the present disclosure includes a mixture of a halogen-containing acid, hydrogen peroxide, and water. Water is present in the mixture in an amount of greater than 90% by volume of the entire mixture. The present disclosure also provides a method of making such a chemical etchant. The method includes mixing, in any order, a halogen-containing acid and hydrogen peroxide to provide a halogen-containing acid/hydrogen peroxide mixture, and adding water to the halogen-containing acid/hydrogen peroxide mixture. Also disclosed is a method of etching a Ge or Ge-rich SiGe alloy utilizing the chemical etchant of the present application.
    Type: Application
    Filed: February 4, 2013
    Publication date: June 13, 2013
    Applicants: S.O.I.TEC SILICON ON INSULATOR TECHNOLOGIES, INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: International Business Machines Corporation, S.O. I. Tec Silicon on Insulator Technologies
  • Publication number: 20130078785
    Abstract: A method for trimming a structure obtained by bonding a first wafer to a second waver on contact faces and thinning the first waver, wherein at least either the first wafer or the second wafer is chamfered and thus exposes the edge of the contact face of the first wafer, wherein the trimming concerns the first wafer. The method includes a) selecting the second wafer from among wafers with a resistance to a chemical etching planned in b) that is sufficient with respect to the first wafer to allow b) to be carried out; b) after bonding the first wafer to the second wafer, chemical etching the edge of the first wafer to form in the first wafer a pedestal resting entirely on the contact face of the second wafer and supporting the remaining of the first wafer; and c) thinning the first wafer until the pedestal is reached and attacked, to provide a thinned part of the first wafer.
    Type: Application
    Filed: November 20, 2012
    Publication date: March 28, 2013
    Applicants: Commissariat A L' Energie Atomique, S.O.I Tec Silicon on Insulator Technologies
    Inventors: S.O.I Tec Silicon on Insulator Technologies, Commissariat A L' Energie Atomique