Patents by Inventor S. Ram Ramaswamy

S. Ram Ramaswamy has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method for providing a fill pattern for an integrated circuit design
    Patent number: 6609235
    Abstract: A method for providing a fill pattern for integrated circuit designs is disclosed. A keepout file having keepout data is generated from a chip design layout file having chip design layout data. The keepout file includes a map of areas of an integrated circuit design where fill patterns cannot be placed. The map of areas from the keepout file is then overlaid with a fill pattern to yield a fill-pattern file. Fill patterns from the fill-pattern file is removed from locations that coincide with locations as defined by the keepout data to yield a final-fill file with crucial fill pattern data. The crucial fill pattern data from the final-fill file is overlaid on the design layout data in the chip design layout file to yield a complete design layout file. Finally, the design rule integrity and logical to physical correspondence of the complete design layout file is verified.
    Type: Grant
    Filed: June 22, 2001
    Date of Patent: August 19, 2003
    Assignee: Bae Systems Information and Electronic Systems Integration, Inc.
    Inventors: S. Ram Ramaswamy, Charles N. Alcorn, Arnett J. Brown, III, Tatia E. Butts
  • Method for providing a fill pattern for an integrated circuit design
    Publication number: 20020199162
    Abstract: A method for providing a fill pattern for integrated circuit designs is disclosed. A keepout file having keepout data is generated from a chip design layout file having chip design layout data. The keepout file includes a map of areas of an integrated circuit design where fill patterns cannot be placed. The map of areas from the keepout file is then overlaid with a fill pattern to yield a fill-pattern file. Fill patterns from the fill-pattern file is removed from locations that coincide with locations as defined by the keepout data to yield a final-fill file with crucial fill pattern data. The crucial fill pattern data from the final-fill file is overlaid on the design layout data in the chip design layout file to yield a complete design layout file. Finally, the design rule integrity and logical to physical correspondence of the complete design layout file is verified.
    Type: Application
    Filed: June 22, 2001
    Publication date: December 26, 2002
    Applicant: BAE Systems
    Inventors: S. Ram Ramaswamy, Charles N. Alcorn, Arnett J. Brown, Tatia B. Butts