Patents by Inventor S. Reji Kumar

S. Reji Kumar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Dual clock domain deskew circuit
    Patent number: 7656983
    Abstract: In general, in one aspect, the disclosure describes an apparatus including a first deskew unit and a second deskew unit. The first deskew unit operates at a first clock domain and provides fine timing adjustment to a signal. The second deskew unit operates at a second clock domain that is slower than the first clock domain and provide coarse timing adjustment to the signal.
    Type: Grant
    Filed: September 29, 2006
    Date of Patent: February 2, 2010
    Assignee: Intel Corporation
    Inventors: Daniel S. Klowden, S. Reji Kumar, Adarsh Panikkar, Kersi H. Vakil, Abhimanyu Kolla
  • Training pattern based de-skew mechanism and frame alignment
    Patent number: 7500131
    Abstract: Some embodiments of the invention provide a training sequence that may be used in a deskewing process or a protocol to be implemented in a training sequence deskew. Embodiments may also comprise a training pattern that allows for header or frame alignment.
    Type: Grant
    Filed: September 7, 2004
    Date of Patent: March 3, 2009
    Assignee: Intel Corporation
    Inventors: Adarsh Panikkar, S. Reji Kumar, Daniel Klowden, Abhimanyu Kolla
  • Selective tracking of serial communication link data
    Publication number: 20080130815
    Abstract: Embodiments to selectively track serial communication link data are presented herein.
    Type: Application
    Filed: December 5, 2006
    Publication date: June 5, 2008
    Inventors: S. Reji Kumar, Arnaud Forestier, Adarsh Panikkar, Kersi H. Vakil
  • Dual clock domain deskew circuit
    Publication number: 20080080654
    Abstract: In general, in one aspect, the disclosure describes an apparatus including a first deskew unit and a second deskew unit. The first deskew unit operates at a first clock domain and provides fine timing adjustment to a signal. The second deskew unit operates at a second clock domain that is slower than the first clock domain and provide coarse timing adjustment to the signal.
    Type: Application
    Filed: September 29, 2006
    Publication date: April 3, 2008
    Inventors: Daniel S. Klowden, S. Reji Kumar, Adarsh Panikkar, Kersi H. Vakil, Abhimanyu Kolla
  • Delaying lanes in order to align all lanes crossing between two clock domains
    Patent number: 7346795
    Abstract: In some embodiments an apparatus and method may comprise a plurality of lanes between two clock domains, each lane comprising circuitry to generate a first signal when the lane may lose cycle coherency with other of the plurality of lanes, generate a second signal to signify a lane has been delayed, and a control circuit coupled with the plurality of lanes to add latency only to lanes that did not generate a second signal if the control circuit detects a first signal from any of the plurality of lanes.
    Type: Grant
    Filed: December 31, 2004
    Date of Patent: March 18, 2008
    Assignee: Intel Corporation
    Inventors: Daniel S. Klowden, Adarsh Panikkar, S. Reji Kumar