Patents by Inventor S V Kalyani MANDALAPU

S V Kalyani MANDALAPU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11418282
    Abstract: The present disclosure provides a transceiver for transmission of data coded according to a Bi-phase Mark Coding (BMC) protocol through a configurable channel (CC) of a USB type-C port. The transceiver includes: a transmitter configured to receive the coded BMC data and transmit the coded BMC data through the CC line. The transmitter includes: a low dropout (LDO) regulator configured to receive a reference voltage (VREF) and generate a local programmable supply voltage; a delay control logic configured to receive the BMC data, and including flipflops connected in series, wherein, output from each flipflop is delayed with respect to input received by the flipflop; and a transmitter driver configured to receive output from each flipflop of the delay control logic, the transmitter driver including a NMOS switches and a PMOS switches. The transceiver includes an eye correction receiver configured to receive output from the transmitter driver of the transmitter.
    Type: Grant
    Filed: February 18, 2021
    Date of Patent: August 16, 2022
    Assignee: SILICONCH SYSTEMS PVT LTD
    Inventors: S V Kalyani Mandalapu, Rakesh Kumar Polasa, Shubham Paliwal, Satish Anand Verkila
  • Publication number: 20220085911
    Abstract: The present disclosure provides a transceiver for transmission of data coded according to a Bi-phase Mark Coding (BMC) protocol through a configurable channel (CC) of a USB type-C port. The transceiver includes: a transmitter configured to receive the coded BMC data and transmit the coded BMC data through the CC line. The transmitter includes: a low dropout (LDO) regulator configured to receive a reference voltage (VREF) and generate a local programmable supply voltage; a delay control logic configured to receive the BMC data, and including flipflops connected in series, wherein, output from each flipflop is delayed with respect to input received by the flipflop; and a transmitter driver configured to receive output from each flipflop of the delay control logic, the transmitter driver including a NMOS switches and a PMOS switches. The transceiver includes an eye correction receiver configured to receive output from the transmitter driver of the transmitter.
    Type: Application
    Filed: February 18, 2021
    Publication date: March 17, 2022
    Inventors: S V Kalyani MANDALAPU, Rakesh Kumar POLASA, Shubham PALIWAL, Satish Anand VERKILA