Abstract: A method for sending data, from an upstream device to a downstream device, including sending a piece of data from one among a plurality of virtual channels sharing the same input buffer memory of the downstream device, if this virtual channel uses a number of memory locations of the input buffer memory strictly less than a current ceiling. It further comprises measuring a communication latency between the upstream and downstream devices, and calculating the current ceiling from the measured latency.

Abstract: A method for communication between first and second devices includes the following stages: the first device sends a request to the second device; the second device receives the request; the second device sends the first device a response to the request; the first device receives the response; the second device estimates a period after which it will be able to send the response, as well as, in at least some cases, the following steps: before sending the response, the second device sends an acknowledgement to the first device, the acknowledgement including the estimated period; the first device receives the acknowledgement; the first device calculates a time interval based on the estimated period; the first device allows the time interval to elapse before starting to monitor the arrival of messages to detect the arrival of the response.

Abstract: A method for sending data, from an upstream device to a downstream device, including sending a piece of data from one among a plurality of virtual channels sharing the same input buffer memory of the downstream device, if this virtual channel uses a number of memory locations of the input buffer memory strictly less than a current ceiling. It further comprises measuring a communication latency between the upstream and downstream devices, and calculating the current ceiling from the measured latency.

Abstract: A computer device with synchronization barrier including a memory and a processing unit capable of multiprocess processing on various processors and enabling the parallel execution of blocks by processes, the blocks being associated by groups in successive work steps. The device further includes a hardware circuit with a usable address space to the memory, capable of receiving a call from each process indicating the end of execution of a current block, each call comprising data. The hardware circuit is arranged to authorize the execution of blocks of a later work step when all the blocks of the current work step have been executed. The accessibility to the address space is achieved by segments drawn from the data of each call.

Abstract: The invention has application in implementation of large Symmetric Multiprocessor Systems with a large number of nodes which include processing elements and associated cache memories. The illustrated embodiment of the invention provides for interconnection of a large number of multiprocessor nodes while reducing over the prior art the size of directories for tracking of memory coherency throughout the system. The embodiment incorporates within the memory controller of each node, directory information relating to the current locations of memory blocks which allows for elimination at a higher level in the node controllers of a larger volume of directory information relating to the location of memory blocks. This arrangement thus allows for more efficient implementation of very large multiprocessor computer systems.

Abstract: The present invention relates to a computer device with synchronization barrier. The device comprises a memory and a processing unit, capable of multiprocess processing on various processors and enabling the parallel execution of blocks by processes, said blocks being associated by groups in successive work steps, The device further comprises a hardware circuit with a usable address space to the memory, capable of receiving a call from each process indicating the end of execution of a current block, each call comprising data. The hardware circuit is arranged to authorize the execution of blocks of a later work step when all the blocks of the current work step have been executed. The accessibility to the address space is achieved by segments drawn from the data of each call.

Abstract: The invention has application in implementation of large Symmetric Multiprocessor Systems with a large number of nodes which include processing elements and associated cache memories. The illustrated embodiment of the invention provides for interconnection of a large number of multiprocessor nodes while reducing over the prior art the size of directories for tracking of memory coherency throughout the system. The embodiment incorporates within the memory controller of each node, directory information relating to the current locations of memory blocks which allows for elimination at a higher level in the node controllers of a larger volume of directory information relating to the location of memory blocks. This arrangement thus allows for more efficient implementation of very large multiprocessor computer systems.