Patents by Inventor Sa Kyun Rha
Sa Kyun Rha has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7717765Abstract: A flat-type fluorescent lamp device includes a first substrate, a plurality of first and second electrodes arranged on the first substrate at fixed intervals, a first fluorescent layer on an entire surface of the first substrate including the first and second electrodes, a second substrate having a plurality of projection portions for maintaining a uniform gap between the first and second substrates, and a second fluorescent layer on the second substrate except at regions of the projection portions that contact the first substrate.Type: GrantFiled: September 13, 2007Date of Patent: May 18, 2010Assignee: LG Display Co., Ltd.Inventors: Jae Bum Kim, Won Jong Lee, Sa Kyun Rha
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Patent number: 7341497Abstract: A flat-type fluorescent lamp device includes first and second substrates facing each other, a plurality of first electrodes on the first substrate disposed along a first direction, each first electrode having protrusions extending from both sides of the first electrode along the first direction, a plurality of second electrodes on the first substrate, the second electrodes each having concave portions that correspond to the protrusions of the first electrode and convex portions that correspond to regions between the protrusions of the first electrode, a first fluorescent layer on an entire surface of the first substrate including the first and second electrodes, and a second fluorescent layer on the second substrate.Type: GrantFiled: January 9, 2007Date of Patent: March 11, 2008Assignee: LG.Philips LCD Co., Ltd.Inventors: Jae Bum Kim, Won Jong Lee, Sa Kyun Rha
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Patent number: 7279829Abstract: A flat-type fluorescent lamp device includes a first substrate, a plurality of first and second electrodes arranged on the first substrate at fixed intervals, a first fluorescent layer on an entire surface of the first substrate including the first and second electrodes, a second substrate having a plurality of projection portions for maintaining a uniform gap between the first and second substrates, and a second fluorescent layer on the second substrate except at regions, of the projection portions that contact the first substrate.Type: GrantFiled: December 30, 2003Date of Patent: October 9, 2007Assignee: LG.Philips LCD Co., Ltd.Inventors: Jae Bum Kim, Won Jong Lee, Sa Kyun Rha
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Patent number: 7183704Abstract: A flat-type fluorescent lamp device includes first and second substrates facing each other, a plurality of first electrodes on the first substrate disposed along a first direction, each first electrode having protrusions extending from both sides of the first electrode along the first direction, a plurality of second electrodes on the first substrate, the second electrodes each having concave portions that correspond to the protrusions of the first electrode and convex portions that correspond to regions between the protrusions of the first electrode, a first fluorescent layer on an entire surface of the first substrate including the first and second electrodes, and a second fluorescent layer on the second substrate.Type: GrantFiled: December 30, 2003Date of Patent: February 27, 2007Assignee: LG.Philips LCD Co., Ltd.Inventors: Jae Bum Kim, Won Jong Lee, Sa Kyun Rha
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Publication number: 20040150318Abstract: A flat-type fluorescent lamp device includes a first substrate, a plurality of first and second electrodes arranged on the first substrate at fixed intervals, a first fluorescent layer on an entire surface of the first substrate including the first and second electrodes, a second substrate having a plurality of projection portions for maintaining a uniform gap between the first and second substrates, and a second fluorescent layer on the second substrate except at regions, of the projection portions that contact the first substrate.Type: ApplicationFiled: December 30, 2003Publication date: August 5, 2004Applicant: LG. PHILIPS LCD CO., LTD.Inventors: Jae Bum Kim, Won Jong Lee, Sa Kyun Rha
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Publication number: 20040150317Abstract: A flat-type fluorescent lamp device includes first and second substrates facing each other, a plurality of first electrodes on the first substrate disposed along a first direction, each first electrode having protrusions extending from both sides of the first electrode along the first direction, a plurality of second electrodes on the first substrate, the second electrodes each having concave portions that correspond to the protrusions of the first electrode and convex portions that correspond to regions between the protrusions of the first electrode, a first fluorescent layer on an entire surface of the first substrate including the first and second electrodes, and a second fluorescent layer on the second substrate.Type: ApplicationFiled: December 30, 2003Publication date: August 5, 2004Applicant: LG.PHILIPS LCD CO., LTD.Inventors: Jae Bum Kim, Won Jong Lee, Sa Kyun Rha
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Patent number: 6747404Abstract: A flat type fluorescent lamp that serves as an illuminating unit and a back light of a large sized liquid crystal panel. The flat type fluorescent lamp includes a first substrate, a second substrate, a first electrode formed on the first substrate, the first electrode including a plurality of protrusions, a phosphor layer formed on the second substrate, a second electrode formed on the phosphor layer, and supports selectively formed between the first substrate and the second substrate. A method for manufacturing a flat type fluorescent lamp comprising the steps of forming a first electrode with protrusions at different intervals on a first substrate, forming a barrier layer over an entire surface of the first substrate including the first electrode, forming a phosphor layer on a second substrate, forming a second electrode on the phosphor layer, selectively forming supports between the first substrate and the second substrate and bonding the first substrate to the second substrate.Type: GrantFiled: June 29, 2001Date of Patent: June 8, 2004Assignees: LG.Philips LCD Co., Ltd., Sangnong Enterprise Co., Ltd.Inventor: Sa Kyun Rha
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Patent number: 6613670Abstract: The method of the present invention includes providing a silicon substrate having an impurity region, forming an inter-layer insulating film having a contact hole in the impurity region and forming a titanium film and titanium nitride film in the contact hole. The method of the present invention further includes conducting a heat treatment to cause a reaction between the titanium film and the silicon substrate and forming a tungsten plug on the titanium nitride film in the contact hole. The device of the present invention including the bit lines are made up of a first inter-layer insulating film on the substrate having a first contact hole over the impurity region, a titanium film in the first contact hole, a titanium nitride film on the titanium film, a titanium silicide film on the silicon substrate wherein the titanium silicide film does not include an agglomerate, a tungsten plug on the titanium nitride film in the first contact hole and a circuit element on the first inter-layer insulating film.Type: GrantFiled: November 18, 1999Date of Patent: September 2, 2003Assignee: Hyundai Electronics Industries Co., Ltd.Inventors: Sa Kyun Rha, Jeong Eui Hong, Young Jun Lee
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Publication number: 20020079828Abstract: A flat type fluorescent lamp that serves as an illuminating unit and a back light of a large sized liquid crystal panel. The flat type fluorescent lamp includes a first substrate, a second substrate, a first electrode formed on the first substrate, the first electrode including a plurality of protrusions, a phosphor layer formed on the second substrate, a second electrode formed on the phosphor layer, and supports selectively formed between the first substrate and the second substrate. A method for manufacturing a flat type fluorescent lamp comprising the steps of forming a first electrode with protrusions at different intervals on a first substrate, forming a barrier layer over an entire surface of the first substrate including the first electrode, forming a phosphor layer on a second substrate, forming a second electrode on the phosphor layer, selectively forming supports between the first substrate and the second substrate and bonding the first substrate to the second substrate.Type: ApplicationFiled: June 29, 2001Publication date: June 27, 2002Inventor: Sa Kyun Rha
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Publication number: 20020037644Abstract: The method of the present invention includes providing a silicon substrate having an impurity region, forming an inter-layer insulating film having a contact hole in the impurity region and forming a titanium film and titanium nitride film in the contact hole. The method of the present invention further includes conducting a heat treatment to cause a reaction between the titanium film and the silicon substrate and forming a tungsten plug on the titanium nitride film in the contact hole.Type: ApplicationFiled: November 18, 1999Publication date: March 28, 2002Inventors: SA KYUN RHA, JEONG EUI HONG, YOUNG JUN LEE
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Patent number: 6294462Abstract: A method of manufacturing an interconnection layer for a semiconductor device comprising the steps of forming a conductive pattern near a surface of a semiconductor substrate or on the surface of the semiconductor substrate, forming an insulation layer on a surface of the conductive pattern, forming grooves in the insulation layer exposing portions of the conductive pattern, forming a first barrier layer pattern on an upper surface of the insulation layer and on sidewalls and bottoms of each of the grooves, selectively forming a seed layer on portions of the first barrier layer pattern, selectively forming a copper interconnection layer on the first barrier layer pattern and the seed layer, and forming a second barrier layer on an upper surface and sides of the copper interconnection layer.Type: GrantFiled: August 4, 1998Date of Patent: September 25, 2001Assignee: Hyundai Electronics Industries Co., Ltd.Inventor: Sa Kyun Rha
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Patent number: 6057228Abstract: The present invention relates to a method of forming an interconnection for a semiconductor device using copper. The method of the invention, including the steps of forming an insulating layer having a groove on a semiconductor substrate containing active elements; forming and depositing a copper thin film on the insulating layer including the groove; and reflowing the copper thin film, may reflow the copper thin film deposited on the semiconductor substrate having a high-step surface for less than 30 min. below 450.degree. C., which show improved annealing conditions as compared with the conventional art. In addition, by reducing consumption of thermal energy in accordance with a low-temperature process, copper is restrained from being rapidly diffused through a silicon substrate, electrodes, etc. when forming the interconnection for the semiconductor device, thus improving productivity of the semiconductor devices.Type: GrantFiled: August 26, 1998Date of Patent: May 2, 2000Assignee: LG Semicon Co., Ltd.Inventors: Seung-Yun Lee, Yong-Sup Hwang, Chong-Ook Park, Dong-Won Kim, Sa-Kyun Rha, Jun-Ki Kim
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Patent number: 5818067Abstract: This invention relates to thin film transistors having a sloped drain region suitable for high integrated elements and the method for fabricating the same. The thin film transistor comprising a substrate, a gate pole formed on the central part of the substrate, a semiconductor layer formed to surround the gate pole on the substrate, a side wall spacer formed at one side of the gate pole on the semiconductor layer, and high density impurity regions formed in the semiconductor layer on both sides of the gate pole. The method for fabricating a TFT comprising steps for forming a gate pole on the central part of a substrate, forming a gate insulation film and a semiconductor layer successively on all over the surface of the substrate, forming a side wall spacer only at one side of the gate pole on the semiconductor layer, and forming high density impurity regions in the semiconductor layer on both sides of the gate by ion injecting impurity ions into the semiconductor layer.Type: GrantFiled: November 5, 1997Date of Patent: October 6, 1998Assignee: LG Semicon Co., Ltd.Inventors: Sa Kyun Rha, Young Il Cheon
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Patent number: 5817367Abstract: A method of forming a thin film of copper on a substrate includes a first step of conducting a chemical vapor deposition (CVD) process using a metal organic (MO) source while applying a first bias voltage to the surface of the substrate and a second step of conducting a chemical vapor deposition process using a metal organic source while applying a second bias voltage to the substrate, wherein the second bias voltage is opposite in polarity to the first bias voltage. The process may include a third step of conducting a chemical vapor deposition process using a metal organic source while applying a third bias voltage to the substrate, where the third bias voltage has the same polarity as the first bias voltage.Type: GrantFiled: December 23, 1996Date of Patent: October 6, 1998Assignee: LG Semicon., Ltd.Inventors: Soung Soon Chun, Chong Ook Park, Dong Won Kim, Won Jun Lee, Sa Kyun Rha, Kyung Il Lee
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Patent number: 5763301Abstract: A method for fabricating Thin Film Transistors includes the steps of forming a gate electrode on a substrate, forming a gate insulation film and a semiconductor layer successively on the substrate, forming a sidewall spacer only at one sidewall of the gate electrode on the semiconductor layer, and forming impurity regions in the semiconductor layer on both sidewalls of the gate electrode by ion-injecting impurity ions into the semiconductor layer.Type: GrantFiled: February 5, 1997Date of Patent: June 9, 1998Assignee: LG Semicon Co., Ltd.Inventors: Sa Kyun Rha, Young Il Cheon
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Patent number: 5728604Abstract: A method for making semiconductor thin film transistors (TFTs) having a bottom gate such that the gate electrode is formed in a furrow of an insulating layer, with a gate oxide and body polysilicon formed thereon, thereby allowing the source and drain level to be in a smooth plane parallel with the gate level. Steps that may be included in the disclosed method for fabricating thin film transistors having a bottom gate are: a) forming an insulating layer on a substrate, and forming a furrow by etching the insulating layer at a portion corresponding to where a gate line is to be formed; b) forming a gate line in the furrow by depositing a conductive layer, and etching back the conductive layer; c) forming a gate insulator on the gate line, forming a semiconductor layer on the gate insulator; and d) forming impurity regions at opposite sides of the gate line.Type: GrantFiled: September 13, 1996Date of Patent: March 17, 1998Assignee: Goldstar Electron Co., Ltd.Inventors: Sa Kyun Rha, Jae-sung Roh