Abstract: Auxiliary control is used to reduce the processing load of an engine control computer by directly controlling a fuel injection system of an internal combustion engine. After initial set up, an auxiliary controller is able to control up to eight injectors while only receiving delay times from engine operating events, e.g. power stroke of each associated cylinder, and pulse width time periods defining the activation times for the injectors. The auxiliary controller can also maintain limited engine operation in the event of failure of the engine control computer when the computer is unable to provide updated delay times and pulse width time periods. A delay time and a pulse width time period are continuously calculated by the engine control computer and provided to the auxiliary controller. The most recently received delay time and pulse width time period are then used by the auxiliary controller to control up to eight identified fuel injectors.

Abstract: An electrical power driver system with fault monitoring provision for both a self test mode and a normal operating mode. During the self test mode, the power driver is momentarily actuated during test intervals and its output compared to a predetermined value for providing self test fault indications. Each power driver is sampled and an indication provided of whether the fault is new or old in addition to providing a count of faults. During normal operation, monitoring circuitry provides indications of a plurality of fault types including over temperature, open circuit, short to ground, and short to voltage. A determination is made of whether each fault type is new or old and a count of faults provided. Output formatting provides indications of fault type, fault count, and whether the fault is intermittent or hard.

Abstract: A dual port, random access, read/write memory is provided such that each microprocessor can access shared memory locations without regard to the state of the other microprocessor. Previously known dual port systems use delays, called wait states, or handshaking techniques to control memory acces and to resolve overlapping memory access requests. This invention avoids the need for special timing controls by improving memory response time. Once a valid address is placed on the address bus by the microprocessor, which is recognized by the memory as being within its range of assigned address values, the memory prefetches the data at that address may soon follow. If it does, then the data is placed on the data bus. If it does not, then the prefeteched data is ignored and a write operation takes place for the particular address.