Patents by Inventor Saad P. Monasa

Saad P. Monasa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Encoding additional states in a three-dimensional crosspoint memory architecture
    Patent number: 12249372
    Abstract: A state may be encoded into a memory cell comprising a phase change material (PM) region and a select device (SD) region by: applying a first current in the memory cell over a first time period, wherein the first current applied over the first time period causes the PM region of the memory cell to be placed into an amorphous state and the SD region of the memory cell to be placed into an amorphous state; and applying a second current in the memory cell over a second time period after the first time period, wherein the second current applied over the third time period causes the SD region of the memory cell to be placed into a crystalline state and the PM region of the memory cell to remain in the amorphous state.
    Type: Grant
    Filed: August 20, 2021
    Date of Patent: March 11, 2025
    Assignee: Intel Corporation
    Inventors: Rouhollah Mousavi Iraei, Kiran Pangal, Saad P. Monasa, Mini Goel, Raymond Zeng, Hemant P. Rao
  • ENCODING ADDITIONAL STATES IN A THREE-DIMENSIONAL CROSSPOINT MEMORY ARCHITECTURE
    Publication number: 20230064007
    Abstract: In one embodiment, a state is encoded into a memory cell comprising a phase change material (PM) region and a select device (SD) region by: applying a first current in the memory cell over a first time period, wherein the first current applied over the first time period causes the PM region of the memory cell to be placed into an amorphous state and the SD region of the memory cell to be placed into an amorphous state; and applying a second current in the memory cell over a second time period after the first time period, wherein the second current applied over the third time period causes the SD region of the memory cell to be placed into a crystalline state and the PM region of the memory cell to remain in the amorphous state.
    Type: Application
    Filed: August 20, 2021
    Publication date: March 2, 2023
    Applicant: Intel Corporation
    Inventors: Rouhollah Mousavi Iraei, Kiran Pangal, Saad P. Monasa, Mini Goel, Raymond Zeng, Hemant P. Rao
  • Multi-level memory cell sensing
    Patent number: 7551489
    Abstract: A multi-level cell memory device performs a read by providing a stepped voltage waveform on a wordline, and comparing cell currents to a substantially constant reference current. Prior to the application of the stepped voltage waveform, the wordline may share charge with another circuit node.
    Type: Grant
    Filed: December 28, 2005
    Date of Patent: June 23, 2009
    Assignee: Intel Corporation
    Inventors: Kerry D. Tedrow, Dung Nguyen, Bo Li, Rezaul Haque, Ahsanur Rahman, Saad P. Monasa, Matthew Goldman
  • Multi-stage digital-to-analog converter
    Patent number: 7265698
    Abstract: A multi-stage digital-to-analog converter has been presented. The multi-stage digital-to-analog converter may include a first digital-to-analog stage to output a first voltage and a second voltage in response to a first portion of a digital value, the first voltage being greater than the second voltage by a predetermined value, and a second digital-to-analog stage coupled to the first digital-to-analog stage to receive the first voltage and the second voltage and to generate a third voltage in between the first and the second voltages in response to a second portion of the digital value.
    Type: Grant
    Filed: January 17, 2006
    Date of Patent: September 4, 2007
    Assignee: Intel Corporation
    Inventors: Richard E. Fackenthal, Matthew G. Dayley, Saad P. Monasa
  • Multi-stage digital-to-analog converter
    Patent number: 7034732
    Abstract: A multi-stage digital-to-analog converter has been presented. The multi-stage digital-to-analog converter may include a first digital-to-analog stage to output a first voltage and a second voltage in response to a first portion of a digital value, the first voltage being greater than the second voltage by a predetermined value, and a second digital-to-analog stage coupled to the first digital-to-analog stage to receive the first voltage and the second voltage and to generate a third voltage in between the first and the second voltages in response to a second portion of the digital value.
    Type: Grant
    Filed: December 30, 2004
    Date of Patent: April 25, 2006
    Assignee: Intel Corporation
    Inventors: Richard E. Fackenthal, Matthew G. Dayley, Saad P. Monasa