Abstract: A controller for a boost power factor correction (PFC) converter. The controller is configured to operate the boost PFC converter in multiple operating modes, including a continuous conduction mode (CCM), a transition mode (TM), and a hybrid mode in which the controller operates the converter in both CCM and TM within a same line cycle. An example controller includes a current control loop and a mode transition circuit. The current control loop is configured to compute an inductor current for each of first and second operation modes, based on a current sample taken, for example, during a boost synchronous rectifier conduction period of the converter. The mode transition circuit includes digital logic circuitry and is configured to generate a pulse indicating that one, two or all three of: zero-voltage switching (ZVS) has been achieved; the synchronous rectifier conduction period is active; and/or one of TM or hybrid mode is active.

Abstract: A controller for a boost power factor correction (PFC) converter. The controller is configured to operate the boost PFC converter in multiple operating modes, including a continuous conduction mode (CCM), a transition mode (TM), and a hybrid mode in which the controller operates the converter in both CCM and TM within a same line cycle. An example controller includes a current control loop and a mode transition circuit. The current control loop is configured to compute an inductor current for each of first and second operation modes, based on a current sample taken, for example, during a boost synchronous rectifier conduction period of the converter. The mode transition circuit includes digital logic circuitry and is configured to generate a pulse indicating that one, two or all three of: zero-voltage switching (ZVS) has been achieved; the synchronous rectifier conduction period is active; and/or one of TM or hybrid mode is active.

Abstract: Systems and method herein provide for energy buffering. In one embodiment, a system includes an energy buffer comprising at least two energy storage elements. Each energy storage element is operable to buffer electrical energy. The system also includes a switch module operable to charge a first of the at least two energy storage elements while discharging a second of the at least two energy storage elements, and to discharge the first energy storage element while charging the second energy storage element after charging the first energy storage element. The switched charging of the energy storage elements compensates voltage variations between the energy storage elements to increase available electrical energy from the energy buffer.

Abstract: A capacitive wireless power transfer (WPT) architecture that provides for dynamic (i.e., in motion) and/or stationary power transfer is provided. In various implementations, for example, the capacitive WPT architecture can achieve high power transfer levels at high efficiencies while maintaining fringing field strengths within acceptable safety limits. In one implementation, for example, a multi-module capacitive wireless power transfer system provides a capacitive charging system, such as for, but not limited to, charging electric vehicles (EV). In another implementation, a capacitive wireless power transfer module is provided. The module, for example, comprises a plurality of first coupling plates adapted to be coupled to a power source via an inverter; a plurality of second coupling plates adapted to be coupled to a load and to the plurality of first coupling plates for receiving wireless power and a matching network adapted to provide reactive compensation and gain.

Abstract: SSC energy buffer circuit includes a switching network and a plurality of energy storage capacitors. The switching network may operate at a relatively low switching frequency and can take advantage of soft charging of the energy storage capacitors to reduce loss. Efficiency of the SSC energy buffer circuit can be extremely high compared with the efficiency of other energy buffer circuits. The SSC energy buffer architecture exhibits losses that scale with the amount of energy buffered, such that a relatively high efficiency can be achieved across a desired operating range. Improvements in SSC energy buffer circuits include, in various implementations, the use of ground reference gate drive, the elimination of a separate precharge circuit through control of at least a portion of the switches of the SSC energy buffer circuit, and/or optimized ratio of capacitance values of two or more capacitors in an SSC energy buffer circuit.

Abstract: A capacitive wireless power transfer (WPT) architecture that provides for dynamic (i.e., in motion) and/or stationary power transfer is provided. In various implementations, for example, the capacitive WPT architecture can achieve high power transfer levels at high efficiencies while maintaining fringing field strengths within acceptable safety limits. In one implementation, for example, a multi-module capacitive wireless power transfer system provides a capacitive charging system, such as for, but not limited to, charging electric vehicles (EV). In another implementation, a capacitive wireless power transfer module is provided. The module, for example, comprises a plurality of first coupling plates adapted to be coupled to a power source via an inverter; a plurality of second coupling plates adapted to be coupled to a load and to the plurality of first coupling plates for receiving wireless power and a matching network adapted to provide reactive compensation and gain.

Abstract: SSC energy buffer circuit includes a switching network and a plurality of energy storage capacitors. The switching network may operate at a relatively low switching frequency and can take advantage of soft charging of the energy storage capacitors to reduce loss. Efficiency of the SSC energy buffer circuit can be extremely high compared with the efficiency of other energy buffer circuits. The SSC energy buffer architecture exhibits losses that scale with the amount of energy buffered, such that a relatively high efficiency can be achieved across a desired operating range. Improvements in SSC energy buffer circuits include, in various implementations, the use of ground reference gate drive, the elimination of a separate precharge circuit through control of at least a portion of the switches of the SSC energy buffer circuit, and/or optimized ratio of capacitance values of two or more capacitors in an SSC energy buffer circuit.