Abstract: An integrated processor is provided with a memory control unit having refresh queue logic for refreshing dynamic random access memory (DRAM) banks during idle memory cycles. The refresh queue logic includes a queue counter and allows the refresh requests to be given a lower priority than other memory transactions until the required refresh rate is in danger of being violated. At this lower priority the refresh requests are honored and retired from a refresh queue only in the absence of other memory transactions. In the event that the refresh queue becomes full, top priority is given to the execution of a refresh request. In this case, a refresh request is honored and retired from the queue immediately after the conclusion of the current memory transaction. This queuing mechanism allows the refresh requests to be buffered until idle memory cycles are available or until absolutely necessary to prevent the violation of refresh timing constraints.

Abstract: A computer system is disclosed for selectively invalidating the contents of cache memory in response to the removal, modification, or disabling of system resources, such as for example, an external memory device. The computer system includes an interface unit which defines an address window for the particular system resource. The address window is implemented through the use of a lower address register and an upper address register, which are loaded in response to a lower and upper enable address signal. An upper comparator compares each tag address with the upper address register value, and a lower comparator compares each tag address with the lower address register value. If the tag address falls within the window, it is flushed by the generation of appropriate control signal. In an alternative embodiment, the present invention can be implemented through software by instructions in microcode.