Abstract: A method of making a semiconductor device can include providing a plurality of semiconductor die, wherein each semiconductor die comprises an active surface and a backside opposite the active surface. The method can include forming a build-up interconnect structure that extends over the active surface of each of the plurality of semiconductor die within the wafer, and forming a unique identifying mark for each of the plurality of semiconductor die as part of a layer within the build-up interconnect structure while simultaneously forming the layer of the build-up interconnect structure. The layer of the build-up interconnect structure can comprise both the unique identifying marks for each of the plurality of semiconductor die and functionality for the semiconductor device. Each unique identifying mark can convey a unique identity of its respective semiconductor die. The method can further include singulating the plurality of semiconductor die into a plurality of semiconductor devices.

Abstract: A method of making a semiconductor device can include providing a plurality of semiconductor die, wherein each semiconductor die comprises an active surface and a backside opposite the active surface. The method can include forming a build-up interconnect structure that extends over the active surface of each of the plurality of semiconductor die within the wafer, and forming a unique identifying mark for each of the plurality of semiconductor die as part of a layer within the build-up interconnect structure while simultaneously forming the layer of the build-up interconnect structure. The layer of the build-up interconnect structure can comprise both the unique identifying marks for each of the plurality of semiconductor die and functionality for the semiconductor device. Each unique identifying mark can convey a unique identity of its respective semiconductor die. The method can further include singulating the plurality of semiconductor die into a plurality of semiconductor devices.

Abstract: Reliability qualification vehicles are described with internally generated clock and control signals which may be selected in place of externally generated signals for exercising the vehicle. If implemented in gate-arrays, the vehicle may be contained in different sized packages to test the effects of different size packaging on the vehicle. Substantially all the gates of the vehicle are testable. The vehicle may be operated synchronously and its design enables quick feedback and analysis of faulty portions of a cell library or place and route scheme.

Abstract: Reliability qualification vehicles are described with internally generated clock and control signals which may be selected in place of externally generated signals for exercising the vehicle. If implemented in gate-arrays, the vehicle may be contained in different sized packages to test the effects of different size packaging on the vehicle. Substantially all the gates of the vehicle are testable. The vehicle may be operated synchronously and its design enables quick feedback and analysis of faulty portions of a cell library or place and route scheme.