Abstract: A multi-processor system with dynamic power optimization for an integrated circuit and methods thereof are described. An input rate control signal is generated responsive to at least one input data stream. An output rate control signal is generated responsive to an output of the plurality of processors. The input rate control signal and the output rate control signal are monitored. The at least one input data stream is partitioned in response to the input rate control signal. The partitioned data is distributed to at least a portion of the plurality of processors. The plurality of processors is operated in a plurality of modes responsive to the monitoring.

Abstract: An embodiment of the invention pertains to an integrated circuit that includes at least one data processing circuit that is configured to generate error data. The integrated circuit further includes a nonvolatile memory, and also a controller circuit that is coupled to the at least one data processing circuit and the nonvolatile memory. The controller circuit is configured to detect the error data. The controller circuit automatically initiates a write operation to store the error data in the nonvolatile memory in response to detecting the error data.

Abstract: Testing of a system-on-a-chip having a programmable section and a plurality of high-speed interfaces begins by configuring the programmable section to support a 1st level testing of the plurality of high-speed interfaces. The testing continues by testing one of the plurality of high-speed interfaces at the 1st level of testing via the programmable section. The testing continues by evaluating the tested performance characteristics in accordance with the prescribed performance characteristics of the standard to determine whether the one of the plurality of high-speed interfaces conforms with the standard requirements. When the one of the plurality of high-speed interfaces conforms with the standard requirements, the plurality of high-speed interfaces are configured for a 2nd level testing, where the 1st level testing is more stringent than the 2nd level testing. The testing continues by testing, at the 2nd level, remaining ones of the plurality of high-speed interfaces.

Abstract: An asynchronous FIFO buffer communicates data between first and second clock domains. The FIFO buffer includes a shift register that accepts and shifts out data at a relatively high output frequency required for the second clock domain. The input data is loaded into the shift register in synchronization with the output clock; input data is not loaded into the shift register on each cycle of the output clock, however, because the input clock is slower than the output clock. A clock comparison circuit compares the input and output clocks and tracks the history of data transfers into the shift register to determine whether a given input datum should be loaded into the shift register during a given period of the output clock. The clock comparison circuit writes input datum into the shift register periodically, skipping write cycles as necessary so that input and output data rates match.

Abstract: Testing of a system-on-a-chip having a programmable section and a plurality of high-speed interfaces begins by configuring the programmable section to support a 1st level testing of the plurality of high-speed interfaces. The testing continues by testing one of the plurality of high-speed interfaces at the 1st level of testing via the programmable section. The testing continues by evaluating the tested performance characteristics in accordance with the prescribed performance characteristics of the standard to determine whether the one of the plurality of high-speed interfaces conforms with the standard requirements. When the one of the plurality of high-speed interfaces conforms with the standard requirements, the plurality of high-speed interfaces are configured for a 2nd level testing, where the 1st level testing is more stringent than the 2nd level testing. The testing continues by testing, at the 2nd level, remaining ones of the plurality of high-speed interfaces.

Abstract: An asynchronous FIFO buffer communicates data between an input clock domain and a relatively slow output clock domain. The input clock frequency is not an even multiple of the output clock frequency, so the data transfer is asynchronous. The FIFO buffer includes a collection of input registers, a shift register, and some clock-comparison and write logic that controls the flow of data into, out of, and between these registers. The input data is loaded into the input registers in synchronization with the input clock. The clock-comparison and write logic compares the input and output clock signals and moves the data from the input registers to the shift register at an address value that may vary based on the result of the comparison of the input and output clock signals, skipping write cycles as necessary to avoid shifting data into the shift register faster than the data is shifted out.

Abstract: Testing of a system-on-a-chip having a programmable section and a plurality of high-speed interfaces begins by configuring the programmable section to support a 1st level testing of the plurality of high-speed interfaces. The testing continues by testing one of the plurality of high-speed interfaces at the 1st level of testing via the programmable section. The testing continues by evaluating the tested performance characteristics in accordance with the prescribed performance characteristics of the standard to determine whether the one of the plurality of high-speed interfaces conforms with the standard requirements. When the one of the plurality of high-speed interfaces conforms with the standard requirements, the plurality of high-speed interfaces are configured for a 2nd level testing, where the 1st level testing is more stringent than the 2nd level testing. The testing continues by testing, at the 2nd level, remaining ones of the plurality of high-speed interfaces.

Abstract: A bridge circuit disposed between a device under test (DUT) and conventional automatic test equipment (ATE) extends the performance of the ATE. The bridge circuit allows the ATE to test ICs capable of operating at frequencies above the ATE's normal performance limits. In some embodiments, the bridge circuit also extends ATE functionality, providing frame alignment and automatic test-vector generation, for example, and can increase the number of available test channels.