Abstract: A method and program-load circuit is for regulating the voltages at the drain and body terminals of a non-volatile memory cell being programmed. These voltages are applied from a program-load circuit connected in a conduction pattern to transfer a predetermined voltage value to at least one terminal of the memory cell. The method includes a step of regulating the voltage value locally, within the program-load circuit, to overcome the effect of a parasitic resistor present in the conduction pattern.

Abstract: A flash memory with a page erase architecture using a local decoding scheme instead of the global decoding scheme known in the prior art. Under the local decoding scheme, the flash memory is partitioned into sections. Each section comprises a plurality of local decoder and local circuitry. The local circuitry comprises switches controlled by the global decoders and these switches switch only in erase operation and not read operation. The reading time is not affected. Each local decoder is coupled to each row of the memory array. Each local decoder comprises a PMOS transistor for passing negative voltages and two NMOS transistors for passing positive voltages so that a page erase is achieved and unselected rows can be protected from unwanted erasure without additional and complex circuitry. The global decoder is located outside of the sectors and provides global signals to all sectors via the local circuitry, thus saving area.

Abstract: A DAC-based voltage regulator system for a non-volatile memory device comprises a charge pump circuit having an enable input and a voltage output node. A voltage-to-current converter has an input coupled to the voltage output node and an output coupled to a virtual ground node. A current source is coupled to the virtual ground node and sinks one of a plurality of currents in response to states of a plurality of digital input signals. A transconductance amplifier has an inverting input at the virtual ground node, a non-inverting input coupled to a reference voltage potential, and an output. A comparator has a first input coupled to the output of the transconductance amplifier, a second input coupled to a reference voltage potential, and an output coupled to the enable input of said charge pump.

Abstract: A flash memory with a new page erase architecture using a local decoding scheme instead of the global decoding scheme known in the prior art. The new architecture saves more die area for memory cells and prevents unwanted erasure without affecting the reading time. Under the local decoding scheme, the flash memory is partitioned into sections. Each section comprises a plurality of local decoder and local circuitry. The local circuitry comprises switches controlled by the global decoders and these switches switch only in erase operation and not read operation. The reading time is not affected. Each local decoder is coupled to each row of the memory array. Each local decoder comprises a PMOS transistor for passing negative voltages and two NMOS transistors for passing positive voltages so that a page erase is achieved and unselected rows can be protected from unwanted erasure without additional and complex circuitry.

Abstract: A DAC-based voltage regulator system for a non-volatile memory device comprises a charge pump circuit having an enable input and a voltage output node. A voltage-to-current converter has an input coupled to the voltage output node and an output coupled to a virtual ground node. A current source is coupled to the virtual ground node and sinks one of a plurality of currents in response to states of a plurality of digital input signals. A transconductance amplifier has an inverting input at the virtual ground node, a non-inverting input coupled to a reference voltage potential, and an output. A comparator has a first input coupled to the output of the transconductance amplifier, a second input coupled to a reference voltage potential, and an output coupled to the enable input of said charge pump.

Abstract: A method and program-load circuit is for regulating the voltages at the drain and body terminals of a non-volatile memory cell being programmed. These voltages are applied from a program-load circuit connected in a conduction pattern to transfer a predetermined voltage value to at least one terminal of the memory cell. The method includes a step of regulating the voltage value locally, within the program-load circuit, to overcome the effect of a parasitic resistor present in the conduction pattern.

Abstract: The non volatile memory device integrates, in one and the same chip, the array of memory cells, a voltage regulator which supplies a regulated operating voltage to a selected word line, and a short circuit detecting circuit. The short circuit detecting circuit detects the output voltage of the voltage regulator, which is correlated to the current for biasing the cells of the word line selected. Once settled to the steady state condition, the output current assumes one first value in the absence of short circuits, and one second value in the presence of a short circuit between the word line selected and one or more adjacent word lines. The short circuit detecting circuit compares the output current of the voltage regulator with a reference value and generates at output a short circuit digital signal which indicates the presence or otherwise of a short circuit.