Abstract: A circuit configuration for an integrated semiconductor memory has memory cells which are configured in a matrix-type memory cell array and which are combined to form addressable units of column lines and row lines. A decoder for selecting one of the column lines with a column select signal has a terminal for an input signal for activating the column select signal. A row activation signal serves for activating a row access signal sequence. The terminal for the input signal of the decoder is connected to a signal from the row access signal sequence which indicates that the row access is concluded. Successive signals in the memory access process prevent the column access from taking place before the end of the row access. The memory access is controlled in a self-adjusting manner.

Abstract: A circuit configuration includes two signal path sections that are used to program the delay of a signal path, in particular in DRAMs. The two signal path sections have different delays and can be driven in parallel at the input end. The two signal path sections can be connected to an output terminal via a multiplexer. A selection circuit includes two signal path sections which are connected between supply voltage potentials. The selection circuit has two complimentary transistors which are connected in series and has source-end programmable elements. These transistors can be driven by complimentary control signals. This permits the delay to be programmed flexibly with little expenditure on circuitry.

Abstract: A layout of a sense amplifier configuration for a semiconductor memory is described. The layout has a plurality of read/write amplifiers, extending as strips in the form of rows one under the other, and having NMOS and PMOS transistors. At least one of the two driver transistors is disposed with its doping regions between the associated NMOS or PMOS transistors of the read/write amplifiers. A gate of the driver transistor is configured as a two-strip gate, in order to accelerate the signal evaluation in the sense amplifiers.

Abstract: The integrated memory has a first address path, via which the address terminals are connected to first selection lines of a first group and which has corresponding first lines and a first decoder circuit. In addition, the integrated memory has a second address path, via which the address terminals are connected to first selection lines of a second group and which has corresponding second lines and a second decoder circuit. The first decoder circuit is faster than the second decoder circuit. The first lines have a longer signal propagation time than the second lines.

Abstract: The integrated circuit has an activation decoder whose outputs are connected to the inputs of a command decoder. When an activation signal is at a first logic level, the activation decoder produces at its outputs a command supplied to it from command inputs. When the activation signal is at a second logic level, the activation decoder produces a deactivation command at its outputs irrespective of the command supplied to it from the command inputs. The command decoder does not activate any of its outputs when the deactivation command is being supplied to its inputs. The command decoder activates one of its outputs in each case when a different command is supplied to its inputs.

Abstract: A test method suitable for testing at least one integrated circuit which, on a main area, has contact areas that serve to transfer signals during a first operating mode of the circuit. Only some of the contact areas are contact-connected to test contacts of a test apparatus and the circuit is put into a second operating mode in which the signals which are transferred via at least one of the non-contact-connected contact areas in the first operating mode are transferred via at least one of the contact-connected contact areas.

Abstract: An integrated memory has memory cells which are each connected to a row line to select one of the memory cells and to a column line to read or write a data signal. A row access controller is used to activate one of the row lines to select one of the memory cells and to control a precharging operation to precharge one of the row lines. A precharge command initiates a precharging operation. The precharging operation for an activated row line is triggered by the row access controller when the reading or writing of a data signal has been finished and when a defined time interval, during which the row line must at least be activated, has elapsed since the activation. As a result, a precharging operation of the activated row line is controlled in a self-adjusting manner. A method of operating an integrated memory is also provided.

Abstract: The integrated circuit has a first decoder unit and a second decoder unit D2 connected in parallel with the latter, which decode the input signals fed to them in a different way in each case. The inputs of the second decoder unit D2 are connected to a respective one of the inputs of the first decoder unit D1. n lines L1 to be selected are each connected to a respective one of the outputs of the two decoder units D1, D2. Via their outputs, the first decoder unit D1 and the second decoder unit D2 determine, in a first operating mode and in a second operating mode, respectively, the potentials of the lines L1 to be selected.

Abstract: A read-write mode control method is described in which a waiting time during a reading process can be shortened by conducting a read instruction with auto-precharging in a first circuit part. The first circuit part is separate from a second circuit part used for conducting the write instruction, since a memory controller does not need to insert any wait cycles between a write instruction and an associated activate signal.

Abstract: An integrated memory has a first operating mode, in which, during each write access, only one of the two global amplifiers is active and transmits a datum via one of the local amplifiers to the corresponding bit line. Moreover, the memory has a second operating mode, in which, during each write access, both global amplifiers are simultaneously active and transmit a common datum via in each case at least one of the local amplifiers to the corresponding bit lines.

Abstract: The memory has a bidirectional address counting unit C1; S, which performs a counting operation for the purpose of generating internal column addresses from an external column address A7 . . . 0. In this case, the counting direction is dependent on the burst operating mode and on an address bit A1 of the external column address. Moreover, the memory has a transformation unit C2; SR2, which forwards partial addresses A2 . . . 1′; PA3 . . . 0′ generated by the address counting unit C1; S either unchanged or incremented by the value 1 to the second column decoder CDEC2, in a manner dependent on the burst operating mode and a further address bit A0 of the external column address A7 . . . 0.

Abstract: Each redundant unit of an integrated memory device is assigned respective programmable elements, comparison units, a code converting unit, a logic unit and a multiplexer. Each multiplexer has a first switching state, in which it connects outputs of the first comparison units to first inputs of the logic unit, and a second switching state, in which it connects outputs of the code converting unit to the first inputs of the logic unit. In the second switching state of the multiplexers, each redundant unit is assigned a different address in the unprogrammed state of the programmable elements. Therefore, redundant units can be selected individually for test purposes.

Abstract: An integrated memory has first control lines, which run in the direction of bit lines, and a second control line, which runs in the direction of word lines. First control inputs of in each case at least two switching elements that are connected to different sense amplifiers are connected to the same first control line. The second control inputs of the switching elements are connected to the second control line. The invention makes it possible to reduce the number of first control lines running in the direction of the bit lines.

Abstract: The integrated memory has a column decoder for decoding column addresses and for addressing corresponding bit lines. The memory also has a first column address bus, which is used to transfer first column addresses to the column decoder, and a second column address bus, which is used to transfer second column addresses to the column decoder. The column decoder in each case addresses bit lines which correspond to the first and second column addresses supplied to it.