Abstract: An electronic memory component provides a plurality of access-secured sub-areas. Each access-secured memory sub-area has at least one assigned parameter, for example, an address. The memory encrypts the assigned parameters of the access-secured sub-areas in such a way that on the one hand the security of such devices is increased considerably and on the other hand the associated expense and technical complexity are not too great. The encryption allows access to at least one sub-area dependent on at least one further sub-area.

Abstract: A digital microelectronic circuit comprises a clocked data-processing unit (1) and a converting unit (2) which reads in data present at the output of the data-processing unit, performs a predetermined converting operation on the data and passes on the converted data. The converting unit is realized in an asynchronous logic circuit, such that the period of time for performing the converting operation is shorter than the shortest time interval to the next change of the data present at the output of the data-processing unit. In this way, fast, serial synchronous processes can be parallelized from the point of view of the slow synchronous system in synchronous systems which are slow relative thereto by using asynchronous logics, without a further high-frequency clock system being required.

Abstract: In order to further develop a data processing device, in particular an electronic memory component, comprising a plurality of access-secured sub-areas, in particular a plurality of access-secured memory areas, each having at least one assigned parameter (an, an?1, . . . , a0), in particular address, and a method of encrypting at least one parameter (an, an?1, . . . , a0 ) in particular the address, of at least one access-secured sub-area, in particular at least one access-secured memory area, of at least one data processing device, in particular at least one electronic memory component, in such a way that on the one hand the security of such devices is increased considerably and on the other hand the associated expense and technical complexity are not too great, it is proposed that the parameter (an, an?1, . . . , a0) of at least one sub-area be capable of encryption only in certain areas, i.e. in dependence on least one further sub-area (a?n, a?n?1, . . . , a?1, a?0).

Abstract: A digital microelectronic circuit comprises a clocked data-processing unit (1) and a converting unit (2) which reads in data present at the output of the data-processing unit, performs a predetermined converting operation on the data and passes on the converted data. The converting unit is realized in an asynchronous logic circuit, such that the period of time for performing the converting operation is shorter than the shortest time interval to the next change of the data present at the output of the data-processing unit. In this way, fast, serial synchronous processes can be parallelized from the point of view of the slow synchronous system in synchronous systems which are slow relative thereto by using asynchronous logics, without a further high-frequency clock system being required.