Patents by Inventor Saburo Oikawa

Saburo Oikawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6750477
    Abstract: In a static induction transistor, in addition to a first gate layer (4), a plurality of second gate layers (41) having a shallower depth and a narrower gap therebetween than those of the first gate layer (4) are provided in an area surrounded by the first gate layer (4), thereby an SiC static induction transistor with an excellent off characteristic is realized, while ensuring a required processing accuracy during production thereof.
    Type: Grant
    Filed: April 15, 2002
    Date of Patent: June 15, 2004
    Assignee: Hitachi, Ltd.
    Inventors: Tsutomu Yatsuo, Toshiyuki Ohno, Hidekatsu Onose, Saburo Oikawa
  • Publication number: 20020109145
    Abstract: In a static induction transistor, in addition to a first gate layer (4), a plurality of second gate layers (41) having a shallower depth and a narrower gap therebetween than those of the first gate layer (4) are provided in an area surrounded by the first gate layer (4), thereby an SiC static induction transistor with an excellent off characteristic is realized, while ensuring a required processing accuracy during production thereof.
    Type: Application
    Filed: April 15, 2002
    Publication date: August 15, 2002
    Inventors: Tsutomu Yatsuo, Toshiyuki Ohno, Hidekatsu Onose, Saburo Oikawa
  • Patent number: 6226059
    Abstract: An anodized oxide film of Al is formed on a scanning signal line and a gate electrode. Al—Ta is used as material of each of the scanning signal line and gate electrode. The thickness of the anodized oxide film is set to at least 1,000 angstroms. The fabrication yield and reliability can be improved.
    Type: Grant
    Filed: June 17, 1998
    Date of Patent: May 1, 2001
    Assignee: Hitachi, Ltd.
    Inventors: Hideaki Yamamoto, Haruo Matsumaru, Tetsuaki Suzuki, Mitsuo Nakatani, Michio Tsukii, Akira Sasano, Saburo Oikawa, Ryoji Oritsuki
  • Patent number: 5781255
    Abstract: An anodized oxide film of Al is formed on a scanning signal line and a gate electrode. Al--Ta is used as material of each of the scanning signal line and gate electrode. The thickness of the anodized oxide film is set to 1,000 angstroms or more. The fabrication yield and reliability can be improved.
    Type: Grant
    Filed: October 4, 1996
    Date of Patent: July 14, 1998
    Assignee: Hitachi, Ltd.
    Inventors: Hideaki Yamamoto, Haruo Matsumaru, Tetsuaki Suzuki, Mitsuo Nakatani, Michio Tsukii, Akira Sasano, Saburo Oikawa, Ryoji Oritsuki
  • Patent number: 5589962
    Abstract: An anodized oxide film of Al is formed on a scanning signal line and a gate electrode. An alloy of Al containing Ta and Ti is used as material of each of the scanning signal line and gate electrode. The thickness of the anodized oxide film is set to 1,000 angstroms or more. The fabrication yield and reliability can be improved.
    Type: Grant
    Filed: June 6, 1995
    Date of Patent: December 31, 1996
    Assignee: Hitachi, Ltd.
    Inventors: Hideaki Yamamoto, Haruo Matsumaru, Tetsuaki Suzuki, Mitsuo Nakatani, Michio Tsukii, Akira Sasano, Saburo Oikawa, Ryoji Oritsuki
  • Patent number: 5153702
    Abstract: This invention relates to a thin film semiconductor device and a method for fabricating it, and more particularly a thin film semiconductor device suitably applicable to a display device in an active matrix system and a method for fabricating it. In this invention, the structure of a thin film semiconductor device for improving the characteristic thereof and particularly the structure relative to the dominant orientation of a poly-Si film as an active layer of a thin film transistor (TFT) is disclosed. A method for fabricating a thin film semiconductor device which is capable of forming a poly-Si film at a relatively low process temperature is disclosed. Further, a display device in an active matrix system which provided high performance and high image quality is disclosed. The poly-Si film having a dominant orientation of (111) is formed by forming a poly-Si film on the semiconductor substrate at a temperature up to 570.degree. C. and annealing the substrate at a temperature up to 640.degree. C.
    Type: Grant
    Filed: June 8, 1988
    Date of Patent: October 6, 1992
    Assignee: Hitachi, Ltd.
    Inventors: Takashi Aoyama, Nobutake Konishi, Takaya Suzuki, Kenji Miyata, Saburo Oikawa, Yoshiaki Okajima, Genshiro Kawachi, Eimi Adachi
  • Patent number: 5021855
    Abstract: A gate turn-off thyristor includes a cathode emitter of n-type, a cathode base of p-type, an anode base of n-type and an anode emitter of p-type. A gate electrode is electrically connected to the p cathode base to enclose and define an elemental gate turn-off thyristor region. A plurality of n cathode emitter regions are arranged in proximity to each other in the elemental gate turn-off thyristor region. A highly-doped buried gate region is provided in the p cathode base with the substantially identical configuration for each n cathode emitter regions.
    Type: Grant
    Filed: March 20, 1989
    Date of Patent: June 4, 1991
    Assignee: Hitachi, Ltd.
    Inventors: Saburo Oikawa, Tsutomu Yatsuo, Yukimasa Satou
  • Patent number: 4825270
    Abstract: The present invention relates to a buried gate type gate turn-off thyristor. A low-resistance layer which is buried in a cathode base layer has a multiplicity of small bores below a cathode emitter layer. The distance between each pair of adjacent small bores and the thickness of the low-resistance layer are each set so as to be smaller than the carrier diffusion length in an anode base layer. In an on-state, carries flow through the low-resistance layer, thereby allowing the low-resistance layer to become conductive, and thus lowering the on-state voltage. A reduction in the dimension of the small bores lowers the resistance of the low-resistance layer and hence lowers the gate drawing out resistance, so that the interrupting capacity is improved.
    Type: Grant
    Filed: February 2, 1987
    Date of Patent: April 25, 1989
    Assignee: Hitachi, Ltd.
    Inventors: Yukimasa Satou, Tsutomu Yatsuo, Saburo Oikawa, Isamu Sanpei
  • Patent number: 4713679
    Abstract: A reverse blocking type semiconductor device capable of being rapidly turned off is disclosed in which a semiconductor substrate includes four semiconductor layers in a region sandwiched between a pair of principal surfaces in such a manner that adjacent ones of these layers are different in conductivity type from each other, one outermost layer of the layers is surrounded by the layer adjacent to the one outermost layer, the one outermost layer and the layer adjacent thereto are exposed to one principal surface, a cathode electrode kept in low-resistance contact with one outermost layer, a gate electrode is kept in low-resistance contact with the layer adjacent to the one outermost layer and lies in close proximity to the one outermost layer, an anode electrode is kept in low-resistance contact with the other outermost layer at the other principal surface, and a main operating region of the other outermost layer has an impurity concentration gradient in a direction parallel to the anode electrode.
    Type: Grant
    Filed: October 15, 1985
    Date of Patent: December 15, 1987
    Assignee: Hitachi, Ltd.
    Inventors: Yoshio Terasawa, Saburo Oikawa
  • Patent number: 4651189
    Abstract: A gate turn-off thyristor and a transistor are disclosed, each of which comprises: a semiconductor substrate including at least three semiconductor layers between a pair of principal surfaces, adjacent ones of the semiconductor layers being different in conductivity type from each other, a first one of the semiconductor layers being formed of at least one strip-shaped region with a constant width, a second one of the semiconductor layers being exposed to a first principal surface of the semiconductor substrate together with the strip-shaped region; a first main electrode kept in ohmic contact with the strip-shaped region at the first principal surface; a first control electrode kept in ohmic contact with the second semiconductor layer on one side of the strip-shaped region in the direction of the width thereof and connected directly to a control terminal; a second control electrode kept in ohmic contact with the second semiconductor layer on the other side of the strip-shaped region in the direction of the wi
    Type: Grant
    Filed: December 12, 1984
    Date of Patent: March 17, 1987
    Assignee: Hitachi, Ltd.
    Inventors: Tsutomu Yatsuo, Takahiro Nagano, Saburo Oikawa, Yukimasa Sato, Shin Kimura, Hiroshi Fukui
  • Patent number: 4646122
    Abstract: A semiconductor device such as a transistor or gate turn-off thyristor provided with a control electrode for improving the current cut-off performance, is disclosed in which an emitter layer of a semiconductor substrate is formed of a plurality of strip-shaped regions, a base layer adjacent to the strip-shaped regions is exposed to one principal surface of the semiconductor substrate together with the strip-shaped regions, one main electrode is provided on each strip-shaped region, first and second control electrodes are provided on the base layer, on one and the other sides of each strip-shaped region viewed in the direction of the width thereof, respectively, the other main electrode is provided on the second principal surface of the semiconductor substrate, and a gate terminal is not connected to the first control electrode but connected to the second control electrode, in order to draw out carriers unequally by the first and second control electrodes at a turn-off period.
    Type: Grant
    Filed: March 2, 1984
    Date of Patent: February 24, 1987
    Assignee: Hitachi, Ltd.
    Inventors: Shin Kimura, Hiroshi Fukui, Hisao Amano, Tsutomu Yatsuo, Saburo Oikawa, Takahiro Nagano
  • Patent number: 4626888
    Abstract: In accordance with the present invention, a plurality of strip-shaped emitter layers on the cathode side are radially arranged on one main surface of the semiconductor substrate while forming a plurality of rings. A gate electrode is in ohmic contact with a part of a base layer which surrounds and is adjacent to each of said emitter layers on the cathode side. Between rings formed by said emitter layers on the cathode side, a ring-shaped gate collecting electrode is provided to be connected to said gate electrode. The gate collecting electrode is provided at a position to balance the potential differences produced by gate currents respectively corresponding to inside and outside of said gate collecting electrode.
    Type: Grant
    Filed: November 10, 1983
    Date of Patent: December 2, 1986
    Assignee: Hitachi, Ltd.
    Inventors: Takahiro Nagano, Tsutomu Yatsuo, Saburo Oikawa, Akira Horie
  • Patent number: 4514747
    Abstract: Disclosed is a field controlled thyristor in which a first semiconductor region of N.sup.+ -type, a second semiconductor region of N-type, third semiconductor regions of P-type, a fourth semiconductor region of N.sup.- -type and a fifth semiconductor region of P.sup.+ -type are formed in a semiconductor substrate having two main surfaces, the first, second and third semiconductor regions being exposed in the first main surface and the fifth semiconductor region being exposed in the second main surface; and the third semiconductor regions of P-type are spaced from each other by a predetermined spacing. The third semiconductor regions are connected with surface-exposed semiconductor regions exposed in the first main surface. The impurity concentration in the second semiconductor region decreases from the first semiconductor region toward the third semiconductor region so that a low forward voltage drop can be achieved along with a high reverse blocking voltage.
    Type: Grant
    Filed: March 12, 1982
    Date of Patent: April 30, 1985
    Assignee: Hitachi, Ltd.
    Inventors: Kenji Miyata, Yoshio Terasawa, Saburo Oikawa, Susumu Murakami, Masahiro Okamura
  • Patent number: 4500903
    Abstract: A gate turn-off thyristor in which a cathode-emitter layer is divided into a plurality of strip-like regions which are radially arrayed on a major surface of a semiconductor substrate in a coaxial multi-ring pattern including a plurality of coaxially arrayed rings. The cathode-emitter strips belonging to a given one of the rings have some radial length. The cathode-emitter strips belonging to the inner ring of a coaxial multi-ring pattern have a smaller radial length than that of the cathode-emitter strips constituting the outer ring. A cathode electrode is contacted to the cathode-emitter strip in low resistance ohmic contact. A gate electrode is ohmic contacted with a low resistance to a cathode-base layer located adjacent to the cathode-emitter strip so as to enclose it. An anode electrode is ohmic contacted with a low resistance to the anode-emitter layer. With the structure of GTO, turn-off operation of unit GTO's each including a cathode-emitter strip is equalized.
    Type: Grant
    Filed: June 3, 1982
    Date of Patent: February 19, 1985
    Assignee: Hitachi, Ltd.
    Inventors: Tsutomu Yatsuo, Takahiro Nagano, Saburo Oikawa, Akira Horie
  • Patent number: 4354121
    Abstract: A switching control circuit includes a first field controlled thyristor having a gate and a cathode between which a backward bias voltage source and a second field controlled thyristor are connected in series. Conduction of the second field controlled thyristor is controlled by controlling a voltage applied across the gate and the cathode, thereby to control conduction of the first field controlled thyristor. A large load current can be positively and safely turned on and off by a relatively small control current or voltage.
    Type: Grant
    Filed: July 10, 1981
    Date of Patent: October 12, 1982
    Assignee: Hitachi, Ltd.
    Inventors: Yoshio Terasawa, Kenji Miyata, Saburo Oikawa, Susumu Murakami, Masahiro Okamura, Takuzo Ogawa
  • Patent number: 4329772
    Abstract: Disclosed is an improved method of growing an epitaxial layer preventing auto-doping from a doped region exposed to a surface of a semiconductor substrate. A surface of a semiconductor substrate of one conductivity type is covered with a mask having a predetermined opening. Then, impurity atoms are doped into the substrate through the opening to form a region of the other conductivity type. An epitaxial layer of one conductivity type is deposited over the exposed surface of the substrate with another mask which covers the entire surface of the region and has an area larger than that of the exposed surface of the region. The latter mask prevents auto-doping from the region of the other conductivity type. The process is usable for controlling, for example, channel widths of field effect semiconductor devices uniformly and precisely.
    Type: Grant
    Filed: March 27, 1980
    Date of Patent: May 18, 1982
    Assignee: Hitachi, Ltd.
    Inventors: Saburo Oikawa, Susumu Murakami, Yoshio Terasawa