Abstract: In a power MOSFET, on an N+ drain layer 21 as a substrate, a second N base layer 3 and a first N? base layer 22 are deposited in the order by epitaxial growth. In a surface portion of the layer 22, there are selectively formed a P base region 23, in a surface portion of which an N+ source region 24 is selectively formed. On a channel region in the P base region 23, a gate electrode 26 is formed with a gate insulator film 25 held between. A source electrode 27 and a drain electrode 28 are formed on the N+ source region 24 and on the back of the substrate, respectively. The layer 3 is made to have a thickness equal to or more than ¼ of that of the first N? base layer 22, and an averaged impurity concentration between 1×1015/cm3 and 3×1017/cm3. The thickness can be alternatively given as equal to or more than ½ of a difference between the thickness x shown as x(?m)=VSEB(V)/8 and that of the layer 22, where VSEB is an SEB(Single Event Burnout) voltage of the layer 3.

Abstract: In a power MOSFET, on an N+ drain layer 21 as a substrate, a second N base layer 3 and a first N− base layer 22 are deposited in the order by epitaxial growth. In a surface portion of the layer 22, there are selectively formed a P base region 23, in a surface portion of which an N+ source region 24 is selectively formed. On a channel region in the P base region 23, a gate electrode 26 is formed with a gate insulator film 25 held between. A source electrode 27 and a drain electrode 28 are formed on the N+ source region 24 and on the back of the substrate, respectively. The layer 3 is made to have a thickness equal to or more than ¼ of that of the first N− base layer 22, and an averaged impurity concentration between 1×1015/cm3 and 3×1017/cm3.