Patents by Inventor Saburo Tazaki

Saburo Tazaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6188734
    Abstract: A data reproducing apparatus for reproducing data subjected to convolution by partial response, by using maximum likelihood, includes a memory including a plurality of memory arrays which respectively correspond to plural states that the data can take and each of which has a predetermined number of regions each corresponding to a time point. A detecting device periodically detects, from the data, states before the plural states have been shifted, and a control device causes values respectively representing the detected states before shifting to be sequentially stored in the regions of the memory arrays every time detection is performed by the detection device, causing the values previously stored in the memory arrays to be replaced in accordance with the detected states before shifting, and when all values stored in the regions of the memory arrays corresponding to the same time point match, reproducing the data on the basis of the matching value.
    Type: Grant
    Filed: October 31, 1996
    Date of Patent: February 13, 2001
    Assignee: Canon Kabushiki Kaisha
    Inventors: Saburo Tazaki, Makoto Hiramatsu
  • Patent number: 4523181
    Abstract: Method and apparatus for producing a binary information by a process comprising the steps of: dividing an input binary data sequence which has a predetermined bit cell length into blocks of a first data pattern thereby forming data blocks; converting information of said data blocks of a first data pattern into data blocks of a second data pattern; integrating accumulated charges of said converted data blocks of the second data pattern; and inverting data of a block of said second data pattern at least when said integrated amount is about to exceed a predetermined finite value in the case that an amount of accumulated charge in said second block is not zero, and producing a binary balanced output code from said second data pattern and said inverted data.
    Type: Grant
    Filed: October 28, 1982
    Date of Patent: June 11, 1985
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Saburo Tazaki, Akifumi Ide